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[Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in Mem
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs |
Date: |
Tue, 5 Feb 2019 17:04:53 +0000 |
From: Richard Henderson <address@hidden>
Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: no need to OR in guarded bit status]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 45ba678a7df..be0ec7de2a4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10577,6 +10577,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
bool ttbr1_valid;
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
+ bool guarded = false;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -10756,6 +10757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
}
/* Merge in attributes from table descriptors */
attrs |= nstable << 3; /* NS */
+ guarded = extract64(descriptor, 50, 1); /* GP */
if (param.hpd) {
/* HPD disables all the table attributes except NSTable. */
break;
@@ -10801,6 +10803,10 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
*/
txattrs->secure = false;
}
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
+ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
+ txattrs->target_tlb_bit0 = true;
+ }
if (cacheattrs != NULL) {
if (mmu_idx == ARMMMUIdx_S2NS) {
--
2.20.1
- [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only, (continued)
- [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 12/22] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 06/22] target/arm: Default handling of BTYPE during translation, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 16/22] gdbstub: allow killing QEMU via vKill command, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 11/22] tests/tcg/aarch64: Add pauth smoke test, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs,
Peter Maydell <=
- [Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 13/22] target/arm: Clean TBI for data operations in the translator, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 20/22] hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 17/22] hw/arm/boot: Fix block comment style in arm_load_kernel(), Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 18/22] hw/arm/boot: Factor out "direct kernel boot" code into its own function, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 08/22] target/arm: Set btype for indirect branches, Peter Maydell, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, no-reply, 2019/02/05
- Re: [Qemu-devel] [PULL 00/22] target-arm queue, Peter Maydell, 2019/02/05