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[Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags |
Date: |
Tue, 5 Feb 2019 17:04:51 +0000 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 4 ++++
target/arm/helper.c | 22 +++++++++++++++-------
target/arm/translate-a64.c | 2 ++
4 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 58f99985c24..1ff7197efd5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3052,6 +3052,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2)
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
+FIELD(TBFLAG_A64, BT, 9, 1)
+FIELD(TBFLAG_A64, BTYPE, 10, 2)
static inline bool bswap_code(bool sctlr_b)
{
diff --git a/target/arm/translate.h b/target/arm/translate.h
index bb37d35741c..3d5e8bacacb 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -69,6 +69,10 @@ typedef struct DisasContext {
bool ss_same_el;
/* True if v8.3-PAuth is active. */
bool pauth_active;
+ /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
+ bool bt;
+ /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */
+ uint8_t btype;
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
int c15_cpar;
/* TCG op of the current insn_start. */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d070879894c..45ba678a7df 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13735,6 +13735,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
if (is_a64(env)) {
ARMCPU *cpu = arm_env_get_cpu(env);
+ uint64_t sctlr;
*pc = env->pc;
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
@@ -13779,6 +13780,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
}
+ if (current_el == 0) {
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ sctlr = env->cp15.sctlr_el[1];
+ } else {
+ sctlr = env->cp15.sctlr_el[current_el];
+ }
if (cpu_isar_feature(aa64_pauth, cpu)) {
/*
* In order to save space in flags, we record only whether
@@ -13786,17 +13793,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
* a nop, or "active" when some action must be performed.
* The decision of which action to take is left to a helper.
*/
- uint64_t sctlr;
- if (current_el == 0) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- sctlr = env->cp15.sctlr_el[1];
- } else {
- sctlr = env->cp15.sctlr_el[current_el];
- }
if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
}
}
+
+ if (cpu_isar_feature(aa64_bti, cpu)) {
+ /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
+ if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
+ flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
+ }
+ flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
+ }
} else {
*pc = env->regs[15];
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 0b94d9455b7..a92fd433783 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13840,6 +13840,8 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
+ dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
+ dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
--
2.20.1
- [Qemu-devel] [PULL 10/22] linux-user: Implement PR_PAC_RESET_KEYS, (continued)
- [Qemu-devel] [PULL 10/22] linux-user: Implement PR_PAC_RESET_KEYS, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 21/22] hw/arm/boot: Support DTB autoload for firmware-only boots, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 01/22] target/arm: Introduce isar_feature_aa64_bti, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 15/22] target/arm: Enable TBI for user-only, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 04/22] exec: Add target-specific tlb bits to MemTxAttrs, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 07/22] target/arm: Reset btype for direct branches, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 09/22] target/arm: Enable BTI for -cpu max, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 12/22] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags,
Peter Maydell <=
- [Qemu-devel] [PULL 06/22] target/arm: Default handling of BTYPE during translation, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 16/22] gdbstub: allow killing QEMU via vKill command, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 11/22] tests/tcg/aarch64: Add pauth smoke test, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 13/22] target/arm: Clean TBI for data operations in the translator, Peter Maydell, 2019/02/05
- [Qemu-devel] [PULL 20/22] hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info, Peter Maydell, 2019/02/05