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Re: [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr |
Date: |
Wed, 19 Dec 2018 17:39:40 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:39:06PM -0800, Richard Henderson wrote:
> This is required before changing the representation of the register.
>
> Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
> ---
> target/ppc/helper.h | 1 +
> target/ppc/arch_dump.c | 3 ++-
> target/ppc/int_helper.c | 5 +++++
> target/ppc/translate/vmx-impl.inc.c | 2 +-
> target/ppc/translate_init.inc.c | 2 +-
> 5 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index b3ffe28103..7dbb08b9dd 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -295,6 +295,7 @@ DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
> DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
> DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
> DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
> +DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
> DEF_HELPER_3(lvebx, void, env, avr, tl)
> DEF_HELPER_3(lvehx, void, env, avr, tl)
> DEF_HELPER_3(lvewx, void, env, avr, tl)
> diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c
> index c272d0d3d4..f753798789 100644
> --- a/target/ppc/arch_dump.c
> +++ b/target/ppc/arch_dump.c
> @@ -17,6 +17,7 @@
> #include "elf.h"
> #include "sysemu/dump.h"
> #include "sysemu/kvm.h"
> +#include "exec/helper-proto.h"
>
> #ifdef TARGET_PPC64
> #define ELFCLASS ELFCLASS64
> @@ -173,7 +174,7 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg,
> PowerPCCPU *cpu)
> vmxregset->avr[i].u64[1] = cpu->env.vsr[32 + i].u64[1];
> }
> }
> - vmxregset->vscr.u32[3] = cpu_to_dump32(s, cpu->env.vscr);
> + vmxregset->vscr.u32[3] = cpu_to_dump32(s, helper_mfvscr(&cpu->env));
> }
>
> static void ppc_write_elf_vsxregset(NoteFuncArg *arg, PowerPCCPU *cpu)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 0443f33cd2..75201bbba6 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -475,6 +475,11 @@ void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
> set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
> }
>
> +uint32_t helper_mfvscr(CPUPPCState *env)
> +{
> + return env->vscr;
> +}
> +
> void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> {
> int i;
> diff --git a/target/ppc/translate/vmx-impl.inc.c
> b/target/ppc/translate/vmx-impl.inc.c
> index ab6da3aa55..1c0c461241 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -187,7 +187,7 @@ static void gen_mfvscr(DisasContext *ctx)
> tcg_gen_movi_i64(avr, 0);
> set_avr64(rD(ctx->opcode), avr, true);
> t = tcg_temp_new_i32();
> - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
> + gen_helper_mfvscr(t, cpu_env);
> tcg_gen_extu_i32_i64(avr, t);
> set_avr64(rD(ctx->opcode), avr, false);
> tcg_temp_free_i32(t);
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 292b1df700..353285c6bd 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -9527,7 +9527,7 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t
> *mem_buf, int n)
> return 16;
> }
> if (n == 32) {
> - stl_p(mem_buf, env->vscr);
> + stl_p(mem_buf, helper_mfvscr(env));
> ppc_maybe_bswap_register(env, mem_buf, 4);
> return 4;
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field, (continued)
- [Qemu-devel] [PATCH 34/34] target/ppc: convert vmin* and vmax* to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr, Richard Henderson, 2018/12/18
- Re: [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr,
David Gibson <=
- [Qemu-devel] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 19/34] target/ppc: convert vspltis[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 16/34] target/ppc: move FP and VMX registers into aligned vsr register array, Richard Henderson, 2018/12/18