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Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decod
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From: |
Stefan Markovic |
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Subject: |
Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions |
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Date: |
Tue, 18 Dec 2018 14:21:33 +0000 |
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
>
> Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
> and LXHU instructions. They were for some reason forgotten in
> previous commits. The MXU opcode list and decoding engine should
> be now complete.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> target/mips/translate.c | 140 +++++++++++++++++++++++++++++-----------
> 1 file changed, 102 insertions(+), 38 deletions(-)
Reviewed-by: Stefan Markovic <address@hidden>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e9c23a594b..e0c8d8c2f7 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1663,12 +1663,21 @@ enum {
> * │ 20..18
> * ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
> * │ ├─ 001 ─ OPC_MXU_S32ALN
> - * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
> - * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR
> - * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
> - * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
> - * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
> - * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
> + * │ ├─ 010 ─ OPC_MXU_S32ALNI
> + * │ ├─ 011 ─ OPC_MXU_S32NOR
> + * │ ├─ 100 ─ OPC_MXU_S32AND
> + * │ ├─ 101 ─ OPC_MXU_S32OR
> + * │ ├─ 110 ─ OPC_MXU_S32XOR
> + * │ └─ 111 ─ OPC_MXU_S32LUI
> + * │
> + * │ 7..5
> + * ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
> + * │ ├─ 001 ─ OPC_MXU_LXH
> + * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW
> + * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU
> + * ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU
> + * ├─ 101100 ─ OPC_MXU_S16LDI
> + * ├─ 101101 ─ OPC_MXU_S16SDI
> * ├─ 101110 ─ OPC_MXU_S32M2I
> * ├─ 101111 ─ OPC_MXU_S32I2M
> * ├─ 110000 ─ OPC_MXU_D32SLL
> @@ -1678,15 +1687,15 @@ enum {
> * ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV
> * ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV
> * │ ├─ 100 ─ OPC_MXU_Q16SLRV
> - * ├─ 110110 ─ OPC_MXU__POOL17 ─┴─ 101 ─ OPC_MXU_Q16SARV
> + * ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV
> * │
> * ├─ 110111 ─ OPC_MXU_Q16SAR
> * │ 23..22
> - * ├─ 111000 ─ OPC_MXU__POOL18 ─┬─ 00 ─ OPC_MXU_Q8MUL
> + * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
> * │ └─ 01 ─ OPC_MXU_Q8MULSU
> * │
> * │ 20..18
> - * ├─ 111001 ─ OPC_MXU__POOL19 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
> + * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
> * │ ├─ 001 ─ OPC_MXU_Q8MOVN
> * │ ├─ 010 ─ OPC_MXU_D16MOVZ
> * │ ├─ 011 ─ OPC_MXU_D16MOVN
> @@ -1694,7 +1703,7 @@ enum {
> * │ └─ 101 ─ OPC_MXU_S32MOV
> * │
> * │ 23..22
> - * ├─ 111010 ─ OPC_MXU__POOL20 ─┬─ 00 ─ OPC_MXU_Q8MAC
> + * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
> * │ └─ 10 ─ OPC_MXU_Q8MACSU
> * ├─ 111011 ─ OPC_MXU_Q16SCOP
> * ├─ 111100 ─ OPC_MXU_Q8MADL
> @@ -1750,7 +1759,7 @@ enum {
> OPC_MXU_S8SDI = 0x25,
> OPC_MXU__POOL15 = 0x26,
> OPC_MXU__POOL16 = 0x27,
> - OPC_MXU_LXB = 0x28,
> + OPC_MXU__POOL17 = 0x28,
> /* not assigned 0x29 */
> OPC_MXU_S16LDD = 0x2A,
> OPC_MXU_S16STD = 0x2B,
> @@ -1764,11 +1773,11 @@ enum {
> OPC_MXU_D32SAR = 0x33,
> OPC_MXU_Q16SLL = 0x34,
> OPC_MXU_Q16SLR = 0x35,
> - OPC_MXU__POOL17 = 0x36,
> + OPC_MXU__POOL18 = 0x36,
> OPC_MXU_Q16SAR = 0x37,
> - OPC_MXU__POOL18 = 0x38,
> - OPC_MXU__POOL19 = 0x39,
> - OPC_MXU__POOL20 = 0x3A,
> + OPC_MXU__POOL19 = 0x38,
> + OPC_MXU__POOL20 = 0x39,
> + OPC_MXU__POOL21 = 0x3A,
> OPC_MXU_Q16SCOP = 0x3B,
> OPC_MXU_Q8MADL = 0x3C,
> OPC_MXU_S32SFL = 0x3D,
> @@ -1940,6 +1949,17 @@ enum {
> /*
> * MXU pool 17
> */
> +enum {
> + OPC_MXU_LXB = 0x00,
> + OPC_MXU_LXH = 0x01,
> + OPC_MXU_LXW = 0x03,
> + OPC_MXU_LXBU = 0x04,
> + OPC_MXU_LXHU = 0x05,
> +};
> +
> +/*
> + * MXU pool 18
> + */
> enum {
> OPC_MXU_D32SLLV = 0x00,
> OPC_MXU_D32SLRV = 0x01,
> @@ -1950,7 +1970,7 @@ enum {
> };
>
> /*
> - * MXU pool 18
> + * MXU pool 19
> */
> enum {
> OPC_MXU_Q8MUL = 0x00,
> @@ -1958,7 +1978,7 @@ enum {
> };
>
> /*
> - * MXU pool 19
> + * MXU pool 20
> */
> enum {
> OPC_MXU_Q8MOVZ = 0x00,
> @@ -1970,7 +1990,7 @@ enum {
> };
>
> /*
> - * MXU pool 20
> + * MXU pool 21
> */
> enum {
> OPC_MXU_Q8MAC = 0x00,
> @@ -25331,12 +25351,58 @@ static void decode_opc_mxu__pool16(CPUMIPSState
> *env, DisasContext *ctx)
> * Decode MXU pool17
> *
> * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-----------+---------+---------+---+---------+-----+-----------+
> + * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15|
> + * +-----------+---------+---------+---+---------+-----+-----------+
> + *
> + */
> +static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)
> +{
> + uint32_t opcode = extract32(ctx->opcode, 6, 2);
> +
> + switch (opcode) {
> + case OPC_MXU_LXW:
> + /* TODO: Implement emulation of LXW instruction. */
> + MIPS_INVAL("OPC_MXU_LXW");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + case OPC_MXU_LXH:
> + /* TODO: Implement emulation of LXH instruction. */
> + MIPS_INVAL("OPC_MXU_LXH");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + case OPC_MXU_LXHU:
> + /* TODO: Implement emulation of LXHU instruction. */
> + MIPS_INVAL("OPC_MXU_LXHU");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + case OPC_MXU_LXB:
> + /* TODO: Implement emulation of LXB instruction. */
> + MIPS_INVAL("OPC_MXU_LXB");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + case OPC_MXU_LXBU:
> + /* TODO: Implement emulation of LXBU instruction. */
> + MIPS_INVAL("OPC_MXU_LXBU");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + default:
> + MIPS_INVAL("decode_opc_mxu");
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + }
> +}
> +/*
> + *
> + * Decode MXU pool18
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> * +-----------+---------+-----+-------+-------+-------+-----------+
> - * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL17|
> + * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18|
> * +-----------+---------+-----+-------+-------+-------+-----------+
> *
> */
> -static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opcode = extract32(ctx->opcode, 18, 3);
>
> @@ -25380,15 +25446,15 @@ static void decode_opc_mxu__pool17(CPUMIPSState
> *env, DisasContext *ctx)
>
> /*
> *
> - * Decode MXU pool18
> + * Decode MXU pool19
> *
> * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> * +-----------+---+---+-------+-------+-------+-------+-----------+
> - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL18|
> + * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19|
> * +-----------+---+---+-------+-------+-------+-------+-----------+
> *
> */
> -static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opcode = extract32(ctx->opcode, 22, 2);
>
> @@ -25406,15 +25472,15 @@ static void decode_opc_mxu__pool18(CPUMIPSState
> *env, DisasContext *ctx)
>
> /*
> *
> - * Decode MXU pool19
> + * Decode MXU pool20
> *
> * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> * +-----------+---------+-----+-------+-------+-------+-----------+
> - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL19|
> + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20|
> * +-----------+---------+-----+-------+-------+-------+-----------+
> *
> */
> -static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opcode = extract32(ctx->opcode, 18, 3);
>
> @@ -25458,15 +25524,15 @@ static void decode_opc_mxu__pool19(CPUMIPSState
> *env, DisasContext *ctx)
>
> /*
> *
> - * Decode MXU pool20
> + * Decode MXU pool21
> *
> * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> * +-----------+---+---+-------+-------+-------+-------+-----------+
> - * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL20|
> + * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21|
> * +-----------+---+---+-------+-------+-------+-------+-----------+
> *
> */
> -static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opcode = extract32(ctx->opcode, 22, 2);
>
> @@ -25669,10 +25735,8 @@ static void decode_opc_mxu(CPUMIPSState *env,
> DisasContext *ctx)
> case OPC_MXU__POOL16:
> decode_opc_mxu__pool16(env, ctx);
> break;
> - case OPC_MXU_LXB:
> - /* TODO: Implement emulation of LXB instruction. */
> - MIPS_INVAL("OPC_MXU_LXB");
> - generate_exception_end(ctx, EXCP_RI);
> + case OPC_MXU__POOL17:
> + decode_opc_mxu__pool17(env, ctx);
> break;
> case OPC_MXU_S16LDD:
> /* TODO: Implement emulation of S16LDD instruction. */
> @@ -25724,23 +25788,23 @@ static void decode_opc_mxu(CPUMIPSState *env,
> DisasContext *ctx)
> MIPS_INVAL("OPC_MXU_Q16SLR");
> generate_exception_end(ctx, EXCP_RI);
> break;
> - case OPC_MXU__POOL17:
> - decode_opc_mxu__pool17(env, ctx);
> + case OPC_MXU__POOL18:
> + decode_opc_mxu__pool18(env, ctx);
> break;
> case OPC_MXU_Q16SAR:
> /* TODO: Implement emulation of Q16SAR instruction. */
> MIPS_INVAL("OPC_MXU_Q16SAR");
> generate_exception_end(ctx, EXCP_RI);
> break;
> - case OPC_MXU__POOL18:
> - decode_opc_mxu__pool18(env, ctx);
> - break;
> case OPC_MXU__POOL19:
> decode_opc_mxu__pool19(env, ctx);
> break;
> case OPC_MXU__POOL20:
> decode_opc_mxu__pool20(env, ctx);
> break;
> + case OPC_MXU__POOL21:
> + decode_opc_mxu__pool21(env, ctx);
> + break;
> case OPC_MXU_Q16SCOP:
> /* TODO: Implement emulation of Q16SCOP instruction. */
> MIPS_INVAL("OPC_MXU_Q16SCOP");
- [Qemu-devel] [PATCH 0/6] target/mips: Amend MXU support, Aleksandar Markovic, 2018/12/17
- [Qemu-devel] [PATCH 3/6] target/mips: MXU: Improve textual description, Aleksandar Markovic, 2018/12/17
- [Qemu-devel] [PATCH 6/6] target/mips: MXU: Add handlers for an align instruction, Aleksandar Markovic, 2018/12/17
- [Qemu-devel] [PATCH 4/6] target/mips: MXU: Add handlers for logic instructions, Aleksandar Markovic, 2018/12/17
- [Qemu-devel] [PATCH 2/6] target/mips: MXU: Add generic naming for optn2 constants, Aleksandar Markovic, 2018/12/17
- [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Aleksandar Markovic, 2018/12/17
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions,
Stefan Markovic <=
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Janeczek, Craig, 2018/12/27
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Aleksandar Markovic, 2018/12/27
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Janeczek, Craig, 2018/12/27
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Aleksandar Markovic, 2018/12/27
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Janeczek, Craig, 2018/12/27
- Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Aleksandar Markovic, 2018/12/27
[Qemu-devel] [PATCH 5/6] target/mips: MXU: Add handlers for max/min instructions, Aleksandar Markovic, 2018/12/17