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Re: [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to sp
From: |
Alex Williamson |
Subject: |
Re: [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to specify link speed and width |
Date: |
Mon, 17 Dec 2018 18:44:04 -0700 |
On Mon, 17 Dec 2018 20:29:37 -0500
"Michael S. Tsirkin" <address@hidden> wrote:
> On Wed, Dec 12, 2018 at 12:39:43PM -0700, Alex Williamson wrote:
> > Allow users to experimentally specify speed and width values for the
> > generic PCIe root port. Defaults remain at 2.5GT/s & x1 for
> > compatiblity with the intent to only support changing defaults via
> > machine types for now.
> >
> > Note for libvirt testing that pcie-root-port controllers are given
> > default names like "pci.7" which don't play well with using the
> > "-set device.$name.$prop=$value" options accessible to us via
> > <qemu:commandline> options. The solution is to add an <alias> to the
> > pcie-root-port <controller>, for example:
> >
> > <controller type='pci' index='7' model='pcie-root-port'>
> > <model name='pcie-root-port'/>
> > <target chassis='7' port='0x15'/>
> > <alias name='ua-gfx0'/>
> > <address type='pci' domain='0x0000' bus='0x00' slot='0x02'
> > function='0x5'/>
> > </controller>
> >
> > The "ua-" here is a mandatory prefix. We can then use:
> >
> > <qemu:commandline>
> > <qemu:arg value='-set'/>
> > <qemu:arg value='device.ua-gfx0.x-speed=8'/>
> > <qemu:arg value='-set'/>
> > <qemu:arg value='device.ua-gfx0.x-width=16'/>
> > </qemu:commandline>
> >
> > or, without an alias, set globals such as:
> >
> > <qemu:commandline>
> > <qemu:arg value='-global'/>
> > <qemu:arg value='pcie-root-port.x-speed=8'/>
> > <qemu:arg value='-global'/>
> > <qemu:arg value='pcie-root-port.x-width=16'/>
> > </qemu:commandline>
> >
> > Cc: Michael S. Tsirkin <address@hidden>
> > Cc: Marcel Apfelbaum <address@hidden>
> > Tested-by: Geoffrey McRae <address@hidden>
> > Reviewed-by: Eric Auger <address@hidden>
> > Signed-off-by: Alex Williamson <address@hidden>
> > ---
> > hw/pci-bridge/gen_pcie_root_port.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/hw/pci-bridge/gen_pcie_root_port.c
> > b/hw/pci-bridge/gen_pcie_root_port.c
> > index 299de429ec1e..ca5418a89dd2 100644
> > --- a/hw/pci-bridge/gen_pcie_root_port.c
> > +++ b/hw/pci-bridge/gen_pcie_root_port.c
> > @@ -124,6 +124,10 @@ static Property gen_rp_props[] = {
> > res_reserve.mem_pref_32, -1),
> > DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
> > res_reserve.mem_pref_64, -1),
> > + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> > + speed, PCIE_LINK_SPEED_2_5),
> > + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
> > + width, PCIE_LINK_WIDTH_1),
> > DEFINE_PROP_END_OF_LIST()
> > };
> >
>
> Doesn't seem to build.
> Just where is DEFINE_PROP_PCIE_LINK_SPEED defined?
In 3/8:
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 3ab9cd2eb69f..b6758c852e11 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -36,6 +36,8 @@ extern const PropertyInfo qdev_prop_uuid;
extern const PropertyInfo qdev_prop_arraylen;
extern const PropertyInfo qdev_prop_link;
extern const PropertyInfo qdev_prop_off_auto_pcibar;
+extern const PropertyInfo qdev_prop_pcie_link_speed;
+extern const PropertyInfo qdev_prop_pcie_link_width;
#define DEFINE_PROP(_name, _state, _field, _prop, _type) { \
.name = (_name), \
@@ -217,6 +219,12 @@ extern const PropertyInfo qdev_prop_off_auto_pcibar;
#define DEFINE_PROP_OFF_AUTO_PCIBAR(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_off_auto_pcibar, \
OffAutoPCIBAR)
+#define DEFINE_PROP_PCIE_LINK_SPEED(_n, _s, _f, _d) \
+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_speed, \
+ PCIExpLinkSpeed)
+#define DEFINE_PROP_PCIE_LINK_WIDTH(_n, _s, _f, _d) \
+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_width, \
+ PCIExpLinkWidth)
#define DEFINE_PROP_UUID(_name, _state, _field) { \
.name = (_name), \
Did something go wrong applying that patch? I'll double check on my
end. Thanks,
Alex
- [Qemu-devel] [PATCH v5 0/8] pcie: Enhanced link speed and width support, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 1/8] pcie: Create enums for link speed and width, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 2/8] pci: Sync PCIe downstream port LNKSTA on read, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 3/8] qapi: Define PCIe link speed and width properties, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 4/8] pcie: Add link speed and width fields to PCIESlot, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 5/8] pcie: Fill PCIESlot link fields to support higher speeds and widths, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 7/8] vfio/pci: Remove PCIe Link Status emulation, Alex Williamson, 2018/12/12
- [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to specify link speed and width, Alex Williamson, 2018/12/12
[Qemu-devel] [PATCH v5 8/8] pcie: Fast PCIe root ports for new machines, Alex Williamson, 2018/12/12