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[Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_unco
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_uncond_b_reg |
Date: |
Thu, 13 Dec 2018 23:23:55 -0600 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 30086a5d7f..e62d248894 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1982,6 +1982,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
{
unsigned int opc, op2, op3, rn, op4;
TCGv_i64 dst;
+ TCGv_i64 modifier;
opc = extract32(insn, 21, 4);
op2 = extract32(insn, 16, 5);
@@ -1999,12 +2000,44 @@ static void disas_uncond_b_reg(DisasContext *s,
uint32_t insn)
case 2: /* RET */
switch (op3) {
case 0:
+ /* BR, BLR, RET */
if (op4 != 0) {
goto do_unallocated;
}
dst = cpu_reg(s, rn);
break;
+ case 2:
+ case 3:
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (opc == 2) {
+ /* RETAA, RETAB */
+ if (rn != 0x1f || op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ rn = 30;
+ modifier = cpu_X[31];
+ } else {
+ /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
+ if (op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ modifier = new_tmp_a64_zero(s);
+ }
+ if (s->pauth_active) {
+ dst = new_tmp_a64(s);
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+ }
+ } else {
+ dst = cpu_reg(s, rn);
+ }
+ break;
+
default:
goto do_unallocated;
}
@@ -2016,12 +2049,38 @@ static void disas_uncond_b_reg(DisasContext *s,
uint32_t insn)
}
break;
+ case 8: /* BRAA */
+ case 9: /* BLRAA */
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (op3 != 2 || op3 != 3) {
+ goto do_unallocated;
+ }
+ if (s->pauth_active) {
+ dst = new_tmp_a64(s);
+ modifier = cpu_reg_sp(s, op4);
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
+ }
+ } else {
+ dst = cpu_reg(s, rn);
+ }
+ gen_a64_set_pc(s, dst);
+ /* BLRAA also needs to load return address */
+ if (opc == 9) {
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+ }
+ break;
+
case 4: /* ERET */
if (s->current_el == 0) {
goto do_unallocated;
}
switch (op3) {
- case 0:
+ case 0: /* ERET */
if (op4 != 0) {
goto do_unallocated;
}
@@ -2030,6 +2089,27 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
offsetof(CPUARMState, elr_el[s->current_el]));
break;
+ case 2: /* ERETAA */
+ case 3: /* ERETAB */
+ if (!dc_isar_feature(aa64_pauth, s)) {
+ goto do_unallocated;
+ }
+ if (rn != 0x1f || op4 != 0x1f) {
+ goto do_unallocated;
+ }
+ dst = tcg_temp_new_i64();
+ tcg_gen_ld_i64(dst, cpu_env,
+ offsetof(CPUARMState, elr_el[s->current_el]));
+ if (s->pauth_active) {
+ modifier = cpu_X[31];
+ if (op3 == 2) {
+ gen_helper_autia(dst, cpu_env, dst, modifier);
+ } else {
+ gen_helper_autib(dst, cpu_env, dst, modifier);
+ }
+ }
+ break;
+
default:
goto do_unallocated;
}
--
2.17.2
- [Qemu-devel] [PATCH v2 06/27] target/arm: Rearrange decode in disas_data_proc_1src, (continued)
- [Qemu-devel] [PATCH v2 06/27] target/arm: Rearrange decode in disas_data_proc_1src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 09/27] target/arm: Move helper_exception_return to helper-a64.c, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 10/27] target/arm: Add new_pc argument to helper_exception_return, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 02/27] target/arm: Add SCTLR bits through ARMv8.5, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 03/27] target/arm: Add PAuth active bit to tbflags, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 07/27] target/arm: Decode PAuth within disas_data_proc_1src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac), Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 11/27] target/arm: Rearrange decode in disas_uncond_b_reg, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 14/27] target/arm: Move cpu_mmu_index out of line, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_uncond_b_reg,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 17/27] target/arm: Create ARMVAParameters and helpers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 22/27] target/arm: Implement pauth_addpac, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 21/27] target/arm: Implement pauth_auth, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 24/27] target/arm: Add PAuth system registers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 18/27] target/arm: Reuse aa64_va_parameters for setting tbflags, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 25/27] target/arm: Enable PAuth for -cpu max, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 26/27] target/arm: Enable PAuth for user-only, part 2, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 20/27] target/arm: Implement pauth_strip, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 23/27] target/arm: Implement pauth_computepac, Richard Henderson, 2018/12/14