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[Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pa
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac) |
Date: |
Thu, 13 Dec 2018 23:23:56 -0600 |
Not that there are any stores involved, but why argue with ARM's
naming convention.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 62 ++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e62d248894..c57c89d98a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3146,6 +3146,65 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t
insn,
s->be_data | size | MO_ALIGN);
}
+/* PAC memory operations
+ *
+ * 31 30 27 26 24 22 21 12 11 10 5 0
+ * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
+ * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
+ * +------+-------+---+-----+-----+------------+---+---+----+-----+
+ *
+ * Rt: the result register
+ * Rn: base address or SP
+ * Rs: the source register for the operation
+ * V: vector flag (always 0 as of v8.3)
+ * M: clear for key DA, set for key DB
+ * W: pre-indexing flag
+ * S: sign for imm9.
+ */
+static void disas_ldst_pac(DisasContext *s, uint32_t insn,
+ int size, int rt, bool is_vector)
+{
+ int rn = extract32(insn, 5, 5);
+ bool is_wback = extract32(insn, 11, 1);
+ bool use_key_a = !extract32(insn, 23, 1);
+ int offset, memidx;
+ TCGv_i64 tcg_addr, tcg_rt;
+
+ if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (rn == 31) {
+ gen_check_sp_alignment(s);
+ }
+ tcg_addr = read_cpu_reg_sp(s, rn, 1);
+
+ if (s->pauth_active) {
+ if (use_key_a) {
+ gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
+ } else {
+ gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
+ }
+ }
+
+ /* Form the 10-bit signed, scaled offset. */
+ offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
+ offset = sextract32(offset << size, 10 + size, 0);
+ tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
+
+ tcg_rt = cpu_reg(s, rt);
+ memidx = get_mem_index(s);
+ do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
+ /* is_signed */ false, /* extend */ false, memidx,
+ /* iss_valid */ true, /* iss_srt */ rt,
+ /* iss_sf */ true, /* iss_ar */ false);
+
+ if (is_wback) {
+ tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
+ }
+}
+
/* Load/store register (all forms) */
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
{
@@ -3171,6 +3230,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
case 2:
disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
return;
+ default:
+ disas_ldst_pac(s, insn, size, rt, is_vector);
+ return;
}
break;
case 1:
--
2.17.2
- [Qemu-devel] [PATCH v2 01/27] target/arm: Add state for the ARMv8.3-PAuth extension, (continued)
- [Qemu-devel] [PATCH v2 01/27] target/arm: Add state for the ARMv8.3-PAuth extension, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 04/27] target/arm: Add PAuth helpers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 08/27] target/arm: Decode PAuth within disas_data_proc_2src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 05/27] target/arm: Decode PAuth within system hint space, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 06/27] target/arm: Rearrange decode in disas_data_proc_1src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 09/27] target/arm: Move helper_exception_return to helper-a64.c, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 10/27] target/arm: Add new_pc argument to helper_exception_return, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 02/27] target/arm: Add SCTLR bits through ARMv8.5, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 03/27] target/arm: Add PAuth active bit to tbflags, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 07/27] target/arm: Decode PAuth within disas_data_proc_1src, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 13/27] target/arm: Decode Load/store register (pac),
Richard Henderson <=
- [Qemu-devel] [PATCH v2 11/27] target/arm: Rearrange decode in disas_uncond_b_reg, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 14/27] target/arm: Move cpu_mmu_index out of line, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 12/27] target/arm: Decode PAuth within disas_uncond_b_reg, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 15/27] target/arm: Introduce arm_mmu_idx, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 17/27] target/arm: Create ARMVAParameters and helpers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 22/27] target/arm: Implement pauth_addpac, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 21/27] target/arm: Implement pauth_auth, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 24/27] target/arm: Add PAuth system registers, Richard Henderson, 2018/12/14
- [Qemu-devel] [PATCH v2 18/27] target/arm: Reuse aa64_va_parameters for setting tbflags, Richard Henderson, 2018/12/14