[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format |
Date: |
Tue, 6 Nov 2018 11:38:25 +0000 |
In do_ats_write() we construct a PAR value based on the result
of the translation. A comment says "S2WLK and FSTAGE are always
zero, because we don't implement virtualization".
Since we do in fact now implement virtualization, add the missing
code that sets these bits based on the reported ARMMMUFaultInfo.
(These bits are named PTW and S in ARMv8, so we follow that
convention in the new comments in this patch.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0ea95b08151..69f684abd89 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2347,10 +2347,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
par64 |= 1; /* F */
par64 |= (fsr & 0x3f) << 1; /* FS */
- /* Note that S2WLK and FSTAGE are always zero, because we don't
- * implement virtualization and therefore there can't be a stage 2
- * fault.
- */
+ if (fi.stage2) {
+ par64 |= (1 << 9); /* S */
+ }
+ if (fi.s1ptw) {
+ par64 |= (1 << 8); /* PTW */
+ }
}
} else {
/* fsr is a DFSR/IFSR value for the short descriptor
--
2.19.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 2/5] milkymist: Check for failure trying to load BIOS image, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format,
Peter Maydell <=
- [Qemu-devel] [PULL 1/5] target/arm: Remove can't-happen if() from handle_vec_simd_shli(), Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 5/5] target/arm: Fix ATS1Hx instructions, Peter Maydell, 2018/11/06
- [Qemu-devel] [PULL 3/5] hw/arm/exynos4210: Zero memory allocated for Exynos4210State, Peter Maydell, 2018/11/06
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2018/11/06