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[Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() |
Date: |
Sat, 20 Oct 2018 09:14:49 +0200 |
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b542daf844..a3b8792a1a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -306,34 +306,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
-
#define EX_SH(amount) \
static int32_t ex_shift_##amount(int imm) \
{ \
@@ -458,10 +430,6 @@ static void decode_RV32_64G(CPURISCVState *env,
DisasContext *ctx)
rd = GET_RD(ctx->opcode);
switch (op) {
- case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
default:
gen_exception_illegal(ctx);
break;
--
2.19.1
- Re: [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, (continued)
- [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/20
- [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/20