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Re: [Qemu-devel] [PATCH 2/7] target/mips: Add MXU instructions S32I2M an
From: |
Janeczek, Craig |
Subject: |
Re: [Qemu-devel] [PATCH 2/7] target/mips: Add MXU instructions S32I2M and S32M2I |
Date: |
Mon, 27 Aug 2018 12:22:18 +0000 |
https://github.com/MIPS/CI20_mplayer/blob/ci20_mplayer/mxu_as
Sorry I mis-read our comment. The bit layouts were pulled from this script and
validated by visually examining compiled code.
-----Original Message-----
From: Janeczek, Craig
Sent: Monday, August 27, 2018 8:15 AM
To: 'Richard Henderson' <address@hidden>; address@hidden
Cc: address@hidden; address@hidden
Subject: RE: [Qemu-devel] [PATCH 2/7] target/mips: Add MXU instructions S32I2M
and S32M2I
https://www.rockbox.org/wiki/pub/Main/IngenicJz4760B/jz-simd-docs.pdf
I pulled them from here. I also wrote a series of tests which I cross compiled
then ran on both HW and through QEMU. Although I did not submit those tests as
part of this patchset as I am unsure of how to add them into the QEMU test
infrastructure.
-----Original Message-----
From: Richard Henderson <address@hidden>
Sent: Saturday, August 25, 2018 1:07 PM
To: Janeczek, Craig <address@hidden>; address@hidden
Cc: address@hidden; address@hidden
Subject: Re: [Qemu-devel] [PATCH 2/7] target/mips: Add MXU instructions S32I2M
and S32M2I
On 08/24/2018 12:44 PM, Craig Janeczek via Qemu-devel wrote:
> Adds support for emulating the S32I2M and S32M2I MXU instructions.
>
> Signed-off-by: Craig Janeczek <address@hidden>
> ---
> target/mips/translate.c | 55
> +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c index
> 50f0cb558f..381dfad36e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -364,6 +364,9 @@ enum {
> OPC_CLO = 0x21 | OPC_SPECIAL2,
> OPC_DCLZ = 0x24 | OPC_SPECIAL2,
> OPC_DCLO = 0x25 | OPC_SPECIAL2,
> + /* MXU */
> + OPC_MXU_S32I2M = 0x2F | OPC_SPECIAL2,
> + OPC_MXU_S32M2I = 0x2E | OPC_SPECIAL2,
I haven't been able to find any documentation of the bit layout of these
instructions. Any pointers?
> +typedef union {
> + struct {
> + uint32_t op:6;
> + uint32_t xra:5;
> + uint32_t:5;
> + uint32_t rb:5;
> + uint32_t:5;
> + uint32_t special2:6;
> + } S32I2M;
> +
> + struct {
> + uint32_t op:6;
> + uint32_t xra:5;
> + uint32_t:5;
> + uint32_t rb:5;
> + uint32_t:5;
> + uint32_t special2:6;
> + } S32M2I;
> +} MXU_OPCODE;
Do not use bitfields. The layout differs by host compiler.
Use extract32(input, pos, len).
> +
> +/* MXU Instructions */
> +static void gen_mxu(DisasContext *ctx, uint32_t opc) { #ifndef
> +TARGET_MIPS64 /* Only works in 32 bit mode */
> + TCGv t0;
> + t0 = tcg_temp_new();
> + MXU_OPCODE *opcode = (MXU_OPCODE *)&ctx->opcode;
> +
> + switch (opc) {
> + case OPC_MXU_S32I2M:
> + gen_load_gpr(t0, opcode->S32I2M.rb);
> + gen_store_mxu_gpr(t0, opcode->S32I2M.xra);
> + break;
> +
> + case OPC_MXU_S32M2I:
> + gen_load_mxu_gpr(t0, opcode->S32M2I.xra);
> + gen_store_gpr(t0, opcode->S32M2I.rb);
> + break;
> + }
> +
> + tcg_temp_free(t0);
> +#else
> + generate_exception_end(ctx, EXCP_RI); #endif }
There's nothing here (yet, I suppose) that won't compile for MIPS64.
I'd suggest avoiding ifdefs as much as possible.
r~
[Qemu-devel] [PATCH 1/7] target/mips: Add MXU register support, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 4/7] target/mips: Add MXU instruction D16MUL, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 3/7] target/mips: Add MXU instruction S8LDD, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 7/7] target/mips: Add MXU instructions S32LDD and S32LDDR, Craig Janeczek, 2018/08/24