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[Qemu-devel] [PATCH 1/7] target/mips: Add MXU register support
From: |
Craig Janeczek |
Subject: |
[Qemu-devel] [PATCH 1/7] target/mips: Add MXU register support |
Date: |
Fri, 24 Aug 2018 15:44:02 -0400 |
This commit makes the MXU registers and the helper functions for
reading/writing to them. This is required for full MXU instruction
support.
Signed-off-by: Craig Janeczek <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 009202cf64..4b2948a2c8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -170,6 +170,7 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
+ target_ulong mxu_gpr[16];
};
typedef struct CPUMIPSState CPUMIPSState;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bdd880bb77..50f0cb558f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1398,6 +1398,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
+/* MXU registers */
+static TCGv mxu_gpr[16];
+
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
@@ -1517,6 +1520,13 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
+static const char * const mxuregnames[] = {
+ "XR1", "XR2", "XR3", "XR4", "XR5",
+ "XR6", "XR7", "XR8", "XR9", "XR10",
+ "XR11", "XR12", "XR13", "XR14", "XR15",
+ "XR16",
+};
+
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@@ -1550,6 +1560,21 @@ static inline void gen_store_gpr (TCGv t, int reg)
tcg_gen_mov_tl(cpu_gpr[reg], t);
}
+/* MXU General purpose registers moves. */
+static inline void gen_load_mxu_gpr (TCGv t, int reg)
+{
+ if (reg == 0)
+ tcg_gen_movi_tl(t, 0);
+ else
+ tcg_gen_mov_tl(t, mxu_gpr[reg-1]);
+}
+
+static inline void gen_store_mxu_gpr (TCGv t, int reg)
+{
+ if (reg != 0)
+ tcg_gen_mov_tl(mxu_gpr[reg-1], t);
+}
+
/* Moves to/from shadow registers. */
static inline void gen_load_srsgpr (int from, int to)
{
@@ -20742,6 +20767,11 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState,
active_fpu.fcr31),
"fcr31");
+
+ for (i = 0; i < 16; i++)
+ mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState,
active_tc.mxu_gpr[i]),
+ mxuregnames[i]);
}
#include "translate_init.inc.c"
--
2.18.0
[Qemu-devel] [PATCH 1/7] target/mips: Add MXU register support,
Craig Janeczek <=
[Qemu-devel] [PATCH 4/7] target/mips: Add MXU instruction D16MUL, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 3/7] target/mips: Add MXU instruction S8LDD, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 7/7] target/mips: Add MXU instructions S32LDD and S32LDDR, Craig Janeczek, 2018/08/24
[Qemu-devel] [PATCH 5/7] target/mips: Add MXU instruction D16MAC, Craig Janeczek, 2018/08/24