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[Qemu-devel] [PATCH v8 25/87] target/mips: Add emulation of nanoMIPS 16-
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v8 25/87] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions |
Date: |
Mon, 13 Aug 2018 19:52:50 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of nanoMIPS 16-bit arithmetic instructions.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0467339..85ecf23 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16693,6 +16693,131 @@ static inline int decode_gpr_gpr4_zero(int r)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
+ uint32_t op;
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+ int imm;
+
+ /* make sure instructions are on a halfword boundary */
+ if (ctx->base.pc_next & 0x1) {
+ TCGv tmp = tcg_const_tl(ctx->base.pc_next);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_temp_free(tmp);
+ generate_exception_end(ctx, EXCP_AdEL);
+ return 2;
+ }
+
+ op = extract32(ctx->opcode, 10, 6);
+ switch (op) {
+ case NM_P16_MV:
+ break;
+ case NM_P16_SHIFT:
+ break;
+ case NM_P16C:
+ break;
+ case NM_P16_A1:
+ switch (extract32(ctx->opcode, 6, 1)) {
+ case NM_ADDIUR1SP:
+ imm = extract32(ctx->opcode, 0, 6) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P16_A2:
+ switch (extract32(ctx->opcode, 3, 1)) {
+ case NM_ADDIUR2:
+ imm = extract32(ctx->opcode, 0, 3) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, imm);
+ break;
+ case NM_P_ADDIURS5:
+ rt = extract32(ctx->opcode, 5, 5);
+ if (rt != 0) {
+ /* imm = sign_extend(s[3] . s[2:0] , from_nbits = 4) */
+ imm = (sextract32(ctx->opcode, 4, 1) << 3) |
+ (extract32(ctx->opcode, 0, 3));
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rt, imm);
+ }
+ break;
+ }
+ break;
+ case NM_P16_ADDU:
+ switch (ctx->opcode & 0x1) {
+ case NM_ADDU16:
+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+ break;
+ case NM_SUBU16:
+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+ break;
+ }
+ break;
+ case NM_P16_4X4:
+ rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ rt = decode_gpr_gpr4(rt);
+ rs = decode_gpr_gpr4(rs);
+ switch ((extract32(ctx->opcode, 7, 2) & 0x2) |
+ (extract32(ctx->opcode, 3, 1))) {
+ case NM_ADDU4X4:
+ gen_arith(ctx, OPC_ADDU, rt, rs, rt);
+ break;
+ case NM_MUL4X4:
+ gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_LI16:
+ break;
+ case NM_ANDI16:
+ break;
+ case NM_P16_LB:
+ break;
+ case NM_P16_LH:
+ break;
+ case NM_LW16:
+ break;
+ case NM_LWSP16:
+ break;
+ case NM_LW4X4:
+ break;
+ case NM_SW4X4:
+ break;
+ case NM_LWGP16:
+ break;
+ case NM_SWSP16:
+ break;
+ case NM_SW16:
+ break;
+ case NM_SWGP16:
+ break;
+ case NM_BC16:
+ break;
+ case NM_BALC16:
+ break;
+ case NM_BEQZC16:
+ break;
+ case NM_BNEZC16:
+ break;
+ case NM_P16_BR:
+ break;
+ case NM_P16_SR:
+ break;
+ case NM_MOVEP:
+ break;
+ case NM_MOVEPREV:
+ break;
+ default:
+ break;
+ }
+
return 2;
}
--
2.7.4
- [Qemu-devel] [PATCH v8 05/87] target/mips: Fix two instances of shadow variables, (continued)
- [Qemu-devel] [PATCH v8 05/87] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 08/87] target/mips: Add support for availability control via bit XNP, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 01/87] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 02/87] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 09/87] target/mips: Add support for availability control via bit MT, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 11/87] target/mips: Implement CP0 Config1.WR bit functionality, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 06/87] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability control, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 25/87] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v8 12/87] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 14/87] target/mips: Add gen_op_addr_addi(), Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 16/87] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 28/87] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 33/87] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 31/87] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 22/87] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 34/87] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 47/87] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/13
- [Qemu-devel] [PATCH v8 53/87] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/13