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Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH v2] nvic: Change NVIC to support ARMv6-M |
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Date: |
Thu, 19 Jul 2018 17:25:46 +0100 |
On 19 July 2018 at 13:16, Julia Suvorova <address@hidden> wrote:
> The differences from ARMv7-M NVIC are:
> * ARMv6-M only supports up to 32 external interrupts
> (configurable feature already). The ICTR is reserved.
> * Active Bit Register is reserved.
> * ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
>
> Signed-off-by: Julia Suvorova <address@hidden>
> ---
> v2:
> * Added num_prio_bits field
> * AIRCR.PRIGROUP is set as RAZ/WI for Baseline
Applied to target-arm.for-3.1, thanks.
-- PMM