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Re: [Qemu-devel] ?==?utf-8?q? [PATCH v3 5/8] target/mips: Add CP0 BadIn
From: |
Aleksandar Markovic |
Subject: |
Re: [Qemu-devel] ?==?utf-8?q? [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register |
Date: |
Thu, 05 Jul 2018 12:08:16 +0200 |
User-agent: |
SOGoMail 2.3.10 |
Hi, Philippe!
> > @@ -6711,6 +6720,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg,
> > int reg, int sel)
> > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
> > rn = "BadInstrP";
> > break;
> > + case 3:
> > + CP0_CHECK(ctx->bi);
> > + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
>
> I'm unsure re-using gen_mfc0_load32() is enough, shouldn't we zero the
> 16 lower bits?
I contacted Stefan, and he says that you are right - zeroing 16 lower bits
seems to be necessary. We'll hopefully fix this in v4.
Yours,
Aleksandar
- Re: [Qemu-devel] ?==?utf-8?q? [PATCH v3 2/8] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c, (continued)
[Qemu-devel] [PATCH v3 6/8] target/mips: Amend CP0 WatchHi register implementation, Aleksandar Markovic, 2018/07/04
[Qemu-devel] [PATCH v3 7/8] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/07/04
[Qemu-devel] [PATCH v3 8/8] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Aleksandar Markovic, 2018/07/04
Re: [Qemu-devel] [PATCH v3 0/8] target/mips: Maintenance and misc fixes and improvements, no-reply, 2018/07/04