[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 2/5] i386: Add CPUID bit and feature words for I
From: |
Robert Hoo |
Subject: |
Re: [Qemu-devel] [PATCH 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR |
Date: |
Tue, 26 Jun 2018 19:07:42 +0800 |
On Mon, 2018-06-25 at 14:06 +0200, Paolo Bonzini wrote:
> On 25/06/2018 05:39, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo <address@hidden>
> > ---
> > target/i386/cpu.c | 2 +-
> > target/i386/cpu.h | 1 +
> > 2 files changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 1e69e68..3134af4 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -896,7 +896,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]
> > = {
> > NULL, NULL, NULL, NULL,
> > NULL, NULL, NULL, NULL,
> > NULL, NULL, "spec-ctrl", NULL,
> > - NULL, NULL, NULL, "ssbd",
> > + NULL, "arch-capabilities", NULL, "ssbd",
> > },
> > .cpuid_eax = 7,
> > .cpuid_needs_ecx = true, .cpuid_ecx = 0,
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 734a73e..1ef2040 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network
> > Instructions */
> > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply
> > Accumulation Single Precision */
> > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
> > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of
> > RDCL_NO and IBRS_ALL*/
> > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store
> > Bypass Disable */
> >
> > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch
> > Prediction Barrier */
> >
>
> For migration to work, you need to add new "features" corresponding to
> the bits in the MSR, and include them in the Icelake-Server and
> Icelake-Client models. Unfortunately there is no code for this in QEMU
> yet, though the API is there in KVM.
>
> I have just sent the KVM patch to pass the MSR value down to QEMU ("KVM:
> VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR").
>
Thanks Paolo.
> Paolo
[Qemu-devel] [PATCH 4/5] i386: Add CPUID bit for WBNOINVD, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 5/5] i386: Add new CPU model Icelake-{Server, Client}, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 3/5] i386: Add CPUID bit for PCONFIG, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs, Robert Hoo, 2018/06/25