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[Qemu-devel] [PATCH 0/5] Add Icelake CPU model
From: |
Robert Hoo |
Subject: |
[Qemu-devel] [PATCH 0/5] Add Icelake CPU model |
Date: |
Mon, 25 Jun 2018 11:39:16 +0800 |
This patch set defines the new guest CPU models of Icelake.
The first patch adds support of IA32_PRED_CMD MSR (IBPB) and
IA32_ARCH_CAPABILITIES MSR.
Other patches add CPUID bits feature words for new features, like PCONFIG,
WBNOINVD. The final patch defines Icelake-{Server,Client} CPU models.
Robert Hoo (5):
i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
i386: Add CPUID bit for PCONFIG
i386: Add CPUID bit for WBNOINVD
i386: Add new CPU model Icelake-{Server,Client}
target/i386/cpu.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++--
target/i386/cpu.h | 7 +++
target/i386/kvm.c | 27 ++++++++++-
target/i386/machine.c | 40 +++++++++++++++++
4 files changed, 192 insertions(+), 4 deletions(-)
--
1.8.3.1
- [Qemu-devel] [PATCH 0/5] Add Icelake CPU model,
Robert Hoo <=
[Qemu-devel] [PATCH 4/5] i386: Add CPUID bit for WBNOINVD, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 5/5] i386: Add new CPU model Icelake-{Server, Client}, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 3/5] i386: Add CPUID bit for PCONFIG, Robert Hoo, 2018/06/25
[Qemu-devel] [PATCH 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs, Robert Hoo, 2018/06/25