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[Qemu-devel] [PULL 43/43] target/arm: Allow ARMv6-M Thumb2 instructions
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 43/43] target/arm: Allow ARMv6-M Thumb2 instructions |
Date: |
Fri, 15 Jun 2018 15:25:21 +0100 |
From: Julia Suvorova <address@hidden>
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required for future Cortex-M0 support.
Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
[PMM: move armv6m_insn[] and armv6m_mask[] closer to
point of use, and mark 'const'. Check for M-and-not-v7
rather than M-and-6.]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 43 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0ff5edf2cec..f405c82fb24 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9965,7 +9965,8 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t
insn)
* end up actually treating this as two 16-bit insns, though,
* if it's half of a bl/blx pair that might span a page boundary.
*/
- if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
+ if (arm_dc_feature(s, ARM_FEATURE_THUMB2) ||
+ arm_dc_feature(s, ARM_FEATURE_M)) {
/* Thumb2 cores (including all M profile ones) always treat
* 32-bit insns as 32-bit.
*/
@@ -10085,10 +10086,38 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
int conds;
int logic_cc;
- /* The only 32 bit insn that's allowed for Thumb1 is the combined
- * BL/BLX prefix and suffix.
+ /*
+ * ARMv6-M supports a limited subset of Thumb2 instructions.
+ * Other Thumb1 architectures allow only 32-bit
+ * combined BL/BLX prefix and suffix.
*/
- if ((insn & 0xf800e800) != 0xf000e800) {
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
+ !arm_dc_feature(s, ARM_FEATURE_V7)) {
+ int i;
+ bool found = false;
+ const uint32_t armv6m_insn[] = {0xf3808000 /* msr */,
+ 0xf3b08040 /* dsb */,
+ 0xf3b08050 /* dmb */,
+ 0xf3b08060 /* isb */,
+ 0xf3e08000 /* mrs */,
+ 0xf000d000 /* bl */};
+ const uint32_t armv6m_mask[] = {0xffe0d000,
+ 0xfff0d0f0,
+ 0xfff0d0f0,
+ 0xfff0d0f0,
+ 0xffe0d000,
+ 0xf800d000};
+
+ for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) {
+ if ((insn & armv6m_mask[i]) == armv6m_insn[i]) {
+ found = true;
+ break;
+ }
+ }
+ if (!found) {
+ goto illegal_op;
+ }
+ } else if ((insn & 0xf800e800) != 0xf000e800) {
ARCH(6T2);
}
@@ -11009,7 +11038,11 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
}
break;
case 3: /* Special control operations. */
- ARCH(7);
+ if (!arm_dc_feature(s, ARM_FEATURE_V7) &&
+ !(arm_dc_feature(s, ARM_FEATURE_V6) &&
+ arm_dc_feature(s, ARM_FEATURE_M))) {
+ goto illegal_op;
+ }
op = (insn >> 4) & 0xf;
switch (op) {
case 2: /* clrex */
--
2.17.1
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, (continued)
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 27/43] target/arm: Implement SVE vector splice (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 35/43] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 29/43] target/arm: Implement SVE Integer Compare - Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 36/43] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 39/43] iommu: Add IOMMU index concept to IOMMU API, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 32/43] target/arm: Implement SVE Predicate Count Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 40/43] iommu: Add IOMMU index argument to notifier APIs, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 43/43] target/arm: Allow ARMv6-M Thumb2 instructions,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2018/06/15