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[Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Mac
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips |
Date: |
Fri, 15 Jun 2018 15:25:16 +0100 |
From: Cédric Le Goater <address@hidden>
On Macronix chips, two bytes can written to the WRSR. First byte will
configure the status register and the second the configuration
register. It is important to save the configuration value as it
contains the dummy cycle setting when using dual or quad IO mode.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/block/m25p80.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a5ccffb4aae..b0ed8fa4188 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -698,6 +698,7 @@ static void complete_collecting_data(Flash *s)
case MAN_MACRONIX:
s->quad_enable = extract32(s->data[0], 6, 1);
if (s->len > 1) {
+ s->volatile_cfg = s->data[1];
s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
}
break;
--
2.17.1
- [Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP, (continued)
- [Qemu-devel] [PULL 34/43] target/arm: Implement FDUP/DUP, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 31/43] target/arm: Implement SVE Partition Break Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 28/43] target/arm: Implement SVE Select Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 41/43] iommu: Add IOMMU index argument to translate method, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 42/43] exec.c: Handle IOMMUs in address_space_translate_for_iotlb(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 22/43] target/arm: Implement SVE Permute - Interleaving Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 27/43] target/arm: Implement SVE vector splice (predicated), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 35/43] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 29/43] target/arm: Implement SVE Integer Compare - Vectors Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 37/43] aspeed_scu: Implement RNG register, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 38/43] m25p80: add support for two bytes WRSR for Macronix chips,
Peter Maydell <=
- [Qemu-devel] [PULL 36/43] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 39/43] iommu: Add IOMMU index concept to IOMMU API, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 32/43] target/arm: Implement SVE Predicate Count Group, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 40/43] iommu: Add IOMMU index argument to notifier APIs, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 43/43] target/arm: Allow ARMv6-M Thumb2 instructions, Peter Maydell, 2018/06/15
- Re: [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2018/06/15