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[Qemu-devel] [PATCH v1 06/29] target-microblaze: Correct the PVR array s
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 06/29] target-microblaze: Correct the PVR array size |
Date: |
Thu, 3 May 2018 11:18:59 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Correct the PVR array size, there are 13 PVR registers.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 994496515f..2304c24b7d 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -277,7 +277,7 @@ struct CPUMBState {
/* These fields are preserved on reset. */
struct {
- uint32_t regs[16];
+ uint32_t regs[13];
} pvr;
};
--
2.14.1
- [Qemu-devel] [PATCH v1 02/29] target-microblaze: dec_store: Use bool instead of unsigned int, (continued)
- [Qemu-devel] [PATCH v1 02/29] target-microblaze: dec_store: Use bool instead of unsigned int, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 03/29] target-microblaze: compute_ldst_addr: Use bool instead of int, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 04/29] target-microblaze: Fallback to our latest CPU version, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 05/29] target-microblaze: Correct special register array sizes, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 06/29] target-microblaze: Correct the PVR array size,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 09/29] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 08/29] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 10/29] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/03
- [Qemu-devel] [PATCH v1 07/29] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/03