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[Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translat
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c |
Date: |
Wed, 21 Mar 2018 13:47:00 -0700 |
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int
rd, int rs1,
tcg_gen_andi_tl(source2, source2, 0x1F);
tcg_gen_sar_tl(source1, source1, source2);
break;
- /* fall through to SRA */
#endif
case OPC_RISC_SRA:
tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
--
2.7.0
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, (continued)
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 16/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 21/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 22/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 24/24] RISC-V: Remove erroneous comment from translate.c,
Michael Clark <=
- Re: [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/24