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Re: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards
From: |
Igor Mammedov |
Subject: |
Re: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model |
Date: |
Mon, 19 Mar 2018 16:47:40 +0100 |
On Fri, 16 Mar 2018 12:41:20 -0700
Michael Clark <address@hidden> wrote:
> - Model borrowed from target/sh4/cpu.c
> - Rewrote riscv_cpu_list to use object_class_get_list
> - Dropped 'struct RISCVCPUInfo' and used TypeInfo array
> - Replaced riscv_cpu_register_types with DEFINE_TYPES
> - Marked base class as abstract
>
> Cc: Igor Mammedov <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
> ---
[...]
> -static void riscv_cpu_register_types(void)
> +static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
> {
> - const RISCVCPUInfo *info = riscv_cpus;
> + RISCVCPUListState *s = user_data;
> + const char *typename = object_class_get_name(OBJECT_CLASS(data));
> + int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
This also fixes "-cpu" output,
before this patch:
# qemu-system-riscv32 -cpu help
any-riscv-cpu
rv32gcsu-v1.9.1-riscv-cpu
rv32gcsu-v1.10.0-riscv-cpu
rv32imacu-nommu-riscv-cpu
sifive-e31-riscv-cpu
sifive-u34-riscv-cpu
# qemu-system-riscv32 -cpu rv32gcsu-v1.9.1-riscv-cpu
qemu-system-riscv32: unable to find CPU model 'rv32gcsu-v1.9.1-riscv-cpu'
after this patch:
# qemu-system-riscv32 -cpu help
any
rv32gcsu-v1.10.0
rv32gcsu-v1.9.1
rv32imacu-nommu
sifive-e31
sifive-u34
which cpu model matches conversion rules of riscv_cpu_class_by_name()
and matching cpu type is found as expected.
> - type_register_static(&riscv_cpu_type_info);
> + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
> +}
[...]
- [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, (continued)
- [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model,
Igor Mammedov <=
- Re: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup, no-reply, 2018/03/16