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[Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstr
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle |
Date: |
Fri, 16 Mar 2018 12:41:18 -0700 |
These fields are marked WARL in the specification so illegal
writes are silently dropped.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index aa101cc..f8595a6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -200,17 +200,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
break;
}
case CSR_MINSTRET:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
- goto do_illegal;
+ /* minstret is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLE:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
- goto do_illegal;
+ /* mcycle is WARL so unsupported writes are ignored */
+ break;
+#if defined(TARGET_RISCV32)
case CSR_MINSTRETH:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
- goto do_illegal;
+ /* minstreth is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLEH:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
- goto do_illegal;
+ /* mcycleh is WARL so unsupported writes are ignored */
+ break;
+#endif
case CSR_MUCOUNTEREN:
env->mucounteren = val_to_write;
break;
@@ -300,10 +302,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
case CSR_MBADADDR:
env->mbadaddr = val_to_write;
break;
- case CSR_MISA: {
- qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
- goto do_illegal;
- }
+ case CSR_MISA:
+ /* misa is WARL so unsupported writes are ignored */
+ break;
case CSR_PMPCFG0:
case CSR_PMPCFG1:
case CSR_PMPCFG2:
@@ -328,7 +329,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
case CSR_PMPADDR15:
pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write);
break;
- do_illegal:
#endif
default:
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
--
2.7.0
- [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order, (continued)
- [Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle,
Michael Clark <=
- [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup, no-reply, 2018/03/16