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[Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more |
Date: |
Wed, 7 Mar 2018 09:43:48 +1300 |
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 179b6cf..ed9d1db 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -16,8 +16,8 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef HW_SPIKE_H
-#define HW_SPIKE_H
+#ifndef HW_RISCV_SPIKE_H
+#define HW_RISCV_SPIKE_H
#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 9588909..d22f184 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -16,8 +16,8 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef HW_VIRT_H
-#define HW_VIRT_H
+#ifndef HW_RISCV_VIRT_H
+#define HW_RISCV_VIRT_H
typedef struct {
RISCVHartArrayState soc;
--
2.7.0
- Re: [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions from, (continued)
[Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure the emulated rom has space for, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more,
Michael Clark <=
[Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 17/22] RISC-V: Ingore satp writes and return 0 for reads, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/06
[Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional, Michael Clark, 2018/03/06
Re: [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups, Michael Clark, 2018/03/06