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Re: [Qemu-devel] [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC |
Date: |
Fri, 9 Feb 2018 12:28:29 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/09/2018 08:58 AM, Peter Maydell wrote:
> Instead of hardcoding the values of M profile ID registers in the
> NVIC, use the fields in the CPU struct. This will allow us to
> give different M profile CPU types different ID register values.
>
> This commit includes the addition of the missing ID_ISAR5,
> which exists as RES0 in both v7M and v8M.
>
> (The values of the ID registers might be wrong for the M4 --
> this commit leaves the behaviour there unchanged.)
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> hw/intc/armv7m_nvic.c | 30 ++++++++++++++++--------------
> target/arm/cpu.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH v2 07/11] target/arm: Implement writing to CONTROL_NS for v8M, (continued)
- [Qemu-devel] [PATCH v2 07/11] target/arm: Implement writing to CONTROL_NS for v8M, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 04/11] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 08/11] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC, Peter Maydell, 2018/02/09
- Re: [Qemu-devel] [PATCH v2 01/11] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 05/11] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 11/11] target/arm: Implement v8M MSPLIM and PSPLIM registers, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 09/11] target/arm: Add AIRCR to vmstate struct, Peter Maydell, 2018/02/09
- [Qemu-devel] [PATCH v2 06/11] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/09