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Re: [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array |
Date: |
Wed, 3 Jan 2018 16:08:17 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 |
On 01/02/2018 04:44 PM, Michael Clark wrote:
> Holds the state of a heterogenous array of RISC-V hardware threads.
At the moment they are homogeneous, since they are all created from the same
cpu_model. Is that the ultimate intent?
> +static Property riscv_harts_props[] = {
> + DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
> + DEFINE_PROP_STRING("cpu-model", RISCVHartArrayState, cpu_model),
> + DEFINE_PROP_END_OF_LIST(),
> +};
How does num_harts interact with max_cpus and smp_cpus, and thus the related
command-line options?
r~
- [Qemu-devel] [PATCH v1 07/21] RISC-V GDB Stub, (continued)
- [Qemu-devel] [PATCH v1 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/02