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Re: [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation |
Date: |
Wed, 3 Jan 2018 15:47:04 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 |
On 01/02/2018 04:44 PM, Michael Clark wrote:
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 20f3d8c..178af56 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1272,6 +1272,28 @@ static inline void init_thread(struct target_pt_regs
> *regs,
>
> #endif /* TARGET_TILEGX */
>
> +#ifdef TARGET_RISCV
> +
> +#define ELF_START_MMAP 0x80000000
For riscv64 too? Surely closer to ((TASK_SIZE / 3) * 2).
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 71696ed..8900141 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -227,7 +227,7 @@ void cpu_loop(CPUX86State *env)
> cpu_exec_end(cs);
> process_queued_cpu_work(cs);
>
> - switch(trapnr) {
> + switch (trapnr) {
Even though the formatting is wrong, don't change unrelated code.
> + case EXCP_DEBUG:
> + gdbstep:
> + signum = gdb_handlesig(cs, TARGET_SIGTRAP);
> + sigcode = TARGET_TRAP_BRKPT;
> + break;
> + default:
> + EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x -
> aborting\n",
> + trapnr);
> + exit(EXIT_FAILURE);
You will need to handle the generic EXCP_ATOMIC as well.
Though of course you won't see that until you use tcg_gen_atomic_*.
r~
- Re: [Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler, (continued)
- [Qemu-devel] [PATCH v1 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/02
- Re: [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation,
Richard Henderson <=
- [Qemu-devel] [PATCH v1 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 15/21] RISC-V Spike Machines, Michael Clark, 2018/01/02
- [Qemu-devel] [PATCH v1 18/21] SiFive RISC-V PRCI Block, Michael Clark, 2018/01/02