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[Qemu-devel] [PATCH v5 15/17] target/m68k: add andi/ori/eori to SR/CCR
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v5 15/17] target/m68k: add andi/ori/eori to SR/CCR |
Date: |
Tue, 2 Jan 2018 02:10:30 +0100 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target/m68k/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 46 insertions(+), 7 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 1a462064be..ee59b5bad2 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2201,6 +2201,7 @@ DISAS_INSN(arith_im)
TCGv dest;
TCGv addr;
int opsize;
+ bool with_SR = ((insn & 0x3f) == 0x3c);
op = (insn >> 9) & 7;
opsize = insn_opsize(insn);
@@ -2217,32 +2218,73 @@ DISAS_INSN(arith_im)
default:
abort();
}
- SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
+
+ if (with_SR) {
+ /* SR/CCR can only be used with andi/eori/ori */
+ if (op == 2 || op == 3 || op == 6) {
+ disas_undef(env, s, insn);
+ return;
+ }
+ switch (opsize) {
+ case OS_BYTE:
+ src1 = gen_get_ccr(s);
+ break;
+ case OS_WORD:
+ if (IS_USER(s)) {
+ gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ return;
+ }
+ src1 = gen_get_sr(s);
+ break;
+ case OS_LONG:
+ disas_undef(env, s, insn);
+ return;
+ }
+ } else {
+ SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
+ }
dest = tcg_temp_new();
switch (op) {
case 0: /* ori */
tcg_gen_or_i32(dest, src1, im);
- gen_logic_cc(s, dest, opsize);
+ if (with_SR) {
+ gen_set_sr(s, dest, opsize == OS_BYTE);
+ } else {
+ DEST_EA(env, insn, opsize, dest, &addr);
+ gen_logic_cc(s, dest, opsize);
+ }
break;
case 1: /* andi */
tcg_gen_and_i32(dest, src1, im);
- gen_logic_cc(s, dest, opsize);
+ if (with_SR) {
+ gen_set_sr(s, dest, opsize == OS_BYTE);
+ } else {
+ DEST_EA(env, insn, opsize, dest, &addr);
+ gen_logic_cc(s, dest, opsize);
+ }
break;
case 2: /* subi */
tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
tcg_gen_sub_i32(dest, src1, im);
gen_update_cc_add(dest, im, opsize);
set_cc_op(s, CC_OP_SUBB + opsize);
+ DEST_EA(env, insn, opsize, dest, &addr);
break;
case 3: /* addi */
tcg_gen_add_i32(dest, src1, im);
gen_update_cc_add(dest, im, opsize);
tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
set_cc_op(s, CC_OP_ADDB + opsize);
+ DEST_EA(env, insn, opsize, dest, &addr);
break;
case 5: /* eori */
tcg_gen_xor_i32(dest, src1, im);
- gen_logic_cc(s, dest, opsize);
+ if (with_SR) {
+ gen_set_sr(s, dest, opsize == OS_BYTE);
+ } else {
+ DEST_EA(env, insn, opsize, dest, &addr);
+ gen_logic_cc(s, dest, opsize);
+ }
break;
case 6: /* cmpi */
gen_update_cc_cmp(s, src1, im, opsize);
@@ -2251,9 +2293,6 @@ DISAS_INSN(arith_im)
abort();
}
tcg_temp_free(im);
- if (op != 6) {
- DEST_EA(env, insn, opsize, dest, &addr);
- }
tcg_temp_free(dest);
}
--
2.14.3
- Re: [Qemu-devel] [PATCH v5 12/17] target/m68k: implement fsave/frestore, (continued)
- [Qemu-devel] [PATCH v5 17/17] target/m68k: fix m68k_cpu_dump_state(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 03/17] linux-user, m68k: correctly manage SR in context, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 05/17] target/m68k: add CPU_LOG_INT trace, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 11/17] target/m68k: add reset, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 15/17] target/m68k: add andi/ori/eori to SR/CCR,
Laurent Vivier <=
- [Qemu-devel] [PATCH v5 13/17] target/m68k: move CCR/SR functions, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 09/17] target/m68k: softmmu cleanup, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 07/17] target/m68k: add chk and chk2, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 08/17] target/m68k: add move16, Laurent Vivier, 2018/01/01