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[Qemu-devel] [PATCH v5 11/17] target/m68k: add reset
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v5 11/17] target/m68k: add reset |
Date: |
Tue, 2 Jan 2018 02:10:26 +0100 |
The instruction traps if the CPU is not in
Supervisor state but the helper is empty because
there is no easy way to reset all the peripherals
without resetting the CPU itself.
Signed-off-by: Laurent Vivier <address@hidden>
---
target/m68k/helper.c | 7 +++++++
target/m68k/helper.h | 4 ++++
target/m68k/translate.c | 13 +++++++++++++
3 files changed, 24 insertions(+)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 7e50ff5871..f8bd456145 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -707,3 +707,10 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val,
uint32_t acc)
res |= (uint64_t)(val & 0xffff0000) << 16;
env->macc[acc + 1] = res;
}
+
+#if defined(CONFIG_SOFTMMU)
+void HELPER(reset)(CPUM68KState *env)
+{
+ /* FIXME: reset all except CPU */
+}
+#endif
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index eebe52dae5..8d0cad7c6b 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -94,3 +94,7 @@ DEF_HELPER_FLAGS_4(bfchg_mem, TCG_CALL_NO_WG, i32, env, i32,
s32, i32)
DEF_HELPER_FLAGS_4(bfclr_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfset_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32)
+
+#if defined(CONFIG_SOFTMMU)
+DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env)
+#endif
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 2a9a9c8e42..68b67bc0a3 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2762,6 +2762,18 @@ DISAS_INSN(unlk)
tcg_temp_free(src);
}
+#if defined(CONFIG_SOFTMMU)
+DISAS_INSN(reset)
+{
+ if (IS_USER(s)) {
+ gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ return;
+ }
+
+ gen_helper_reset(cpu_env);
+}
+#endif
+
DISAS_INSN(nop)
{
}
@@ -5634,6 +5646,7 @@ void register_m68k_insns (CPUM68KState *env)
#if defined(CONFIG_SOFTMMU)
INSN(move_to_usp, 4e60, fff8, USP);
INSN(move_from_usp, 4e68, fff8, USP);
+ INSN(reset, 4e70, ffff, M68000);
BASE(stop, 4e72, ffff);
BASE(rte, 4e73, ffff);
INSN(movec, 4e7b, ffff, CF_ISA_A);
--
2.14.3
- Re: [Qemu-devel] [PATCH v5 14/17] target/m68k: add 680x0 "move to SR" instruction, (continued)
- [Qemu-devel] [PATCH v5 12/17] target/m68k: implement fsave/frestore, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 17/17] target/m68k: fix m68k_cpu_dump_state(), Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 03/17] linux-user, m68k: correctly manage SR in context, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 05/17] target/m68k: add CPU_LOG_INT trace, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 11/17] target/m68k: add reset,
Laurent Vivier <=
- [Qemu-devel] [PATCH v5 15/17] target/m68k: add andi/ori/eori to SR/CCR, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 13/17] target/m68k: move CCR/SR functions, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 09/17] target/m68k: softmmu cleanup, Laurent Vivier, 2018/01/01
- [Qemu-devel] [PATCH v5 07/17] target/m68k: add chk and chk2, Laurent Vivier, 2018/01/01