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[Qemu-devel] [PULL 07/20] target/arm: Restore security state on exceptio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return |
Date: |
Fri, 6 Oct 2017 16:59:32 +0100 |
Now that we can handle the CONTROL.SPSEL bit not necessarily being
in sync with the current stack pointer, we can restore the correct
security state on exception return. This happens before we start
to read registers off the stack frame, but after we have taken
possible usage faults for bad exception return magic values and
updated CONTROL.SPSEL.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 36173e2..b82fc9f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6381,6 +6381,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
*/
write_v7m_control_spsel(env, return_to_sp_process);
+ switch_v7m_security_state(env, return_to_secure);
+
{
/* The stack pointer we should be reading the exception frame from
* depends on bits in the magic exception return type value (and
--
2.7.4
- [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values, (continued)
- [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 12/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 10/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 08/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 03/20] hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 02/20] hw/sd: fix out-of-bounds check for multi block reads, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return,
Peter Maydell <=
- [Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state", Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 17/20] target/arm: Implement security attribute lookups for memory accesses, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 01/20] arm: Fix SMC reporting to EL2 when QEMU provides PSCI, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 05/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 06/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/10/06
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2017/10/06