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[Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4 |
Date: |
Fri, 29 Sep 2017 22:08:29 -0400 |
This both advertises that we support four counters and adds them to the
implementation because the PMU_NUM_COUNTERS macro reads this value from
the PMCR.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e48bb67..659b2b8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4926,7 +4926,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
+ /* 4 counters enabled */
+ .resetvalue = (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT),
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies,
Inc.\nQualcomm Technologies, Inc. is a member of the\nCode Aurora Forum, a
Linux Foundation Collaborative Project.
- [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0], Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4,
Aaron Lindsay <=
- [Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2017/09/29
- [Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2017/09/29