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[Qemu-devel] [PULL 24/31] target/arm: Make MMFAR banked for v8M
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/31] target/arm: Make MMFAR banked for v8M |
Date: |
Thu, 7 Sep 2017 14:28:17 +0100 |
Make the MMFAR register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 2 +-
hw/intc/armv7m_nvic.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/machine.c | 3 ++-
4 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d223446..03a47de 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -427,7 +427,7 @@ typedef struct CPUARMState {
uint32_t cfsr; /* Configurable Fault Status */
uint32_t hfsr; /* HardFault Status */
uint32_t dfsr; /* Debug Fault Status Register */
- uint32_t mmfar; /* MemManage Fault Address */
+ uint32_t mmfar[2]; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl[2]; /* MPU_CTRL */
int exception;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index a889397..dd0710a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -506,7 +506,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
case 0xd30: /* Debug Fault Status. */
return cpu->env.v7m.dfsr;
case 0xd34: /* MMFAR MemManage Fault Address */
- return cpu->env.v7m.mmfar;
+ return cpu->env.v7m.mmfar[attrs.secure];
case 0xd38: /* Bus Fault Address. */
return cpu->env.v7m.bfar;
case 0xd3c: /* Aux Fault Status. */
@@ -720,7 +720,7 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
cpu->env.v7m.dfsr &= ~value; /* W1C */
break;
case 0xd34: /* Mem Manage Address. */
- cpu->env.v7m.mmfar = value;
+ cpu->env.v7m.mmfar[attrs.secure] = value;
return;
case 0xd38: /* Bus Fault Address. */
cpu->env.v7m.bfar = value;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2fe1662..cd95474 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6375,10 +6375,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
case EXCP_DATA_ABORT:
env->v7m.cfsr |=
(R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK);
- env->v7m.mmfar = env->exception.vaddress;
+ env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT,
"...with CFSR.DACCVIOL and MMFAR 0x%x\n",
- env->v7m.mmfar);
+ env->v7m.mmfar[env->v7m.secure]);
break;
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
diff --git a/target/arm/machine.c b/target/arm/machine.c
index d740e83..7a96986 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m = {
VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
- VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
+ VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU),
VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU),
@@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security = {
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
+ VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST()
}
};
--
2.7.4
- [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region, (continued)
- [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 06/31] xilinx_axidma: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 25/31] target/arm: Make CFSR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 23/31] target/arm: Make CCR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 16/31] target/arm: Make CONTROL register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 26/31] target/arm: Move regime_is_secure() to target/arm/internals.h, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 24/31] target/arm: Make MMFAR banked for v8M,
Peter Maydell <=
- [Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 05/31] xilinx_axienet: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers, Peter Maydell, 2017/09/07
- Re: [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/21