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[Qemu-devel] [PATCH v15 21/32] target/arm: [tcg, a64] Port to breakpoint
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v15 21/32] target/arm: [tcg, a64] Port to breakpoint_check |
Date: |
Mon, 24 Jul 2017 13:27:17 -0700 |
From: Lluís Vilanova <address@hidden>
Incrementally paves the way towards using the generic instruction translation
loop.
Reviewed-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Lluís Vilanova <address@hidden>
Message-Id: <address@hidden>
[rth: Use DISAS_TOO_MANY for "execute only one more" after bp.]
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++----------------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2edcfe05f3..4cb8c66b8d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11246,6 +11246,30 @@ static void aarch64_tr_insn_start(DisasContextBase
*dcbase, CPUState *cpu)
tcg_gen_insn_start(dc->pc, 0, 0);
}
+static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState
*cpu,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ if (bp->flags & BP_CPU) {
+ gen_a64_set_pc_im(dc->pc);
+ gen_helper_check_breakpoints(cpu_env);
+ /* End the TB early; it likely won't be executed */
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ } else {
+ gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
+ /* The address covered by the breakpoint must be
+ included in [tb->pc, tb->pc + tb->size) in order
+ to for it to be properly cleared -- thus we
+ increment the PC here so that the logic setting
+ tb->size below does the right thing. */
+ dc->pc += 4;
+ dc->base.is_jmp = DISAS_NORETURN;
+ }
+
+ return true;
+}
+
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
TranslationBlock *tb)
{
@@ -11282,25 +11306,15 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == dc->pc) {
- if (bp->flags & BP_CPU) {
- gen_a64_set_pc_im(dc->pc);
- gen_helper_check_breakpoints(cpu_env);
- /* End the TB early; it likely won't be executed */
- dc->base.is_jmp = DISAS_UPDATE;
- } else {
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
- /* The address covered by the breakpoint must be
- included in [dc->base.tb->pc, dc->base.tb->pc +
dc->base.tb->size) in order
- to for it to be properly cleared -- thus we
- increment the PC here so that the logic setting
- dc->base.tb->size below does the right thing. */
- dc->pc += 4;
- goto done_generating;
+ if (bp->pc == dc->base.pc_next) {
+ if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) {
+ break;
}
- break;
}
}
+ if (dc->base.is_jmp > DISAS_TOO_MANY) {
+ break;
+ }
}
if (dc->base.num_insns == max_insns && (dc->base.tb->cflags &
CF_LAST_IO)) {
@@ -11371,6 +11385,7 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
} else {
switch (dc->base.is_jmp) {
case DISAS_NEXT:
+ case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, dc->pc);
break;
case DISAS_JUMP:
@@ -11408,7 +11423,6 @@ void gen_intermediate_code_a64(DisasContextBase
*dcbase, CPUState *cs,
}
}
-done_generating:
gen_tb_end(tb, dc->base.num_insns);
#ifdef DEBUG_DISAS
--
2.13.3
- [Qemu-devel] [PATCH v15 10/32] target/i386: [tcg] Port to breakpoint_check, (continued)
- [Qemu-devel] [PATCH v15 10/32] target/i386: [tcg] Port to breakpoint_check, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 13/32] target/i386: [tcg] Port to disas_log, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 12/32] target/i386: [tcg] Port to tb_stop, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 14/32] target/i386: [tcg] Port to generic translation framework, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 16/32] target/arm: [tcg] Port to init_disas_context, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 17/32] target/arm: [tcg, a64] Port to init_disas_context, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 18/32] target/arm: [tcg] Port to tb_start, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 15/32] target/arm: [tcg] Port to DisasContextBase, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 19/32] target/arm: [tcg] Port to insn_start, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 20/32] target/arm: [tcg, a64] Port to insn_start, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 21/32] target/arm: [tcg, a64] Port to breakpoint_check,
Richard Henderson <=
- [Qemu-devel] [PATCH v15 22/32] target/arm: [tcg] Port to translate_insn, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 23/32] target/arm: [tcg, a64] Port to translate_insn, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 24/32] target/arm: [tcg] Port to tb_stop, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 25/32] target/arm: [tcg, a64] Port to tb_stop, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 27/32] target/arm: [tcg, a64] Port to disas_log, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 26/32] target/arm: [tcg] Port to disas_log, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 30/32] target/arm: Move ss check to init_disas_context, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 28/32] target/arm: [tcg] Port to generic translation framework, Richard Henderson, 2017/07/24
- [Qemu-devel] [PATCH v15 29/32] target/arm: [a64] Move page and ss checks to init_disas_context, Richard Henderson, 2017/07/24