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[Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left |
Date: |
Wed, 18 Jan 2017 23:38:31 +0100 |
Implement the behavior described in the chapter 13.9.11 of
UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005:
"If a TLB Data-In replacement is attempted with all TLB
entries locked and valid, the last TLB entry (entry 63) is
replaced."
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/ldst_helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index d3747cf..029120d 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -246,9 +246,11 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
}
#ifdef DEBUG_MMU
- DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
+ DPRINTF_MMU("%s lru replacement: no free entries available, "
+ "replacing the last one\n", strmmu);
#endif
- /* error state? */
+ /* corner case: the last entry is replaced anyway */
+ replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1);
}
#endif
--
2.7.2
- [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers, (continued)
- [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left,
Artyom Tarasenko <=
- [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2017/01/18