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[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs |
Date: |
Wed, 18 Jan 2017 23:38:40 +0100 |
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.
"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"
Integer stores of all sizes are allowed with these ASIs.
Signed-off-by: Artyom Tarasenko <address@hidden>
---
target/sparc/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0f20ed0..655060c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2321,8 +2321,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv
addr,
case GET_ASI_EXCP:
break;
case GET_ASI_DTWINX: /* Reserved for stda. */
+#ifndef TARGET_SPARC64
gen_exception(dc, TT_ILL_INSN);
break;
+#else
+ if (!(dc->def->features & CPU_FEATURE_HYPV)) {
+ /* Pre OpenSPARC CPUs don't have these */
+ gen_exception(dc, TT_ILL_INSN);
+ return;
+ }
+ /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
+ * are ST_BLKINIT_ ASIs */
+ /* fall through */
+#endif
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
--
2.7.2
- [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, (continued)
- [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs,
Artyom Tarasenko <=
- [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2017/01/18
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Peter Maydell, 2017/01/23
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2017/01/23
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Peter Maydell, 2017/01/23
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Artyom Tarasenko, 2017/01/23
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Peter Maydell, 2017/01/23
- Re: [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine, Jakub Jermář, 2017/01/27
[Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c, Artyom Tarasenko, 2017/01/18
Re: [Qemu-devel] [PULL 00/30] target-sparc sun4v support, Peter Maydell, 2017/01/19