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Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts |
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Date: |
Wed, 30 Nov 2016 12:42:09 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 |
On 11/29/2016 03:52 PM, Laurent Vivier wrote:
> It doesn't work because we work with word/byte where the bit sign has
> been extended to the long word. So in the case of 0 shift, with retrieve
> C=<original bit sign> and not 0.
Ah, right. I wonder if it's better to always zero-extend the inputs for
left-shifts, as opposed to needing the movcond.
r~
- [Qemu-devel] [PATCH v2 2/5] target-m68k: Do not cpu_abort on undefined insns, (continued)
[Qemu-devel] [PATCH v2 4/5] target-m68k: Implement bitfield ops for registers, Richard Henderson, 2016/11/09
[Qemu-devel] [PATCH v2 5/5] target-m68k: Implement bitfield ops for memory, Richard Henderson, 2016/11/09
Re: [Qemu-devel] [PATCH v2 0/5] target-m68k-patches, Laurent Vivier, 2016/11/09