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[Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline |
Date: |
Thu, 27 Oct 2016 10:07:26 -0700 |
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0fb361a..3b3389c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2036,6 +2036,8 @@ typedef enum {
GET_ASI_DTWINX,
GET_ASI_BLOCK,
GET_ASI_SHORT,
+ GET_ASI_BCOPY,
+ GET_ASI_BFILL,
} ASIType;
typedef struct {
@@ -2077,6 +2079,14 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
mem_idx = MMU_PHYS_IDX;
type = GET_ASI_DIRECT;
break;
+ case ASI_M_BCOPY: /* Block copy, sta access */
+ mem_idx = MMU_KERNEL_IDX;
+ type = GET_ASI_BCOPY;
+ break;
+ case ASI_M_BFILL: /* Block fill, stda access */
+ mem_idx = MMU_KERNEL_IDX;
+ type = GET_ASI_BFILL;
+ break;
}
} else {
gen_exception(dc, TT_PRIV_INSN);
@@ -2294,6 +2304,38 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv
addr,
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
break;
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+ case GET_ASI_BCOPY:
+ /* Copy 32 bytes from the address in SRC to ADDR. */
+ /* ??? The original qemu code suggests 4-byte alignment, dropping
+ the low bits, but the only place I can see this used is in the
+ Linux kernel with 32 byte alignment, which would make more sense
+ as a cacheline-style operation. */
+ {
+ TCGv s_addr = tcg_temp_new();
+ TCGv d_addr = tcg_temp_new();
+ TCGv four = tcg_const_tl(4);
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ int i;
+
+ tcg_gen_andi_tl(s_addr, src, -4);
+ tcg_gen_andi_tl(d_addr, addr, -4);
+ for (i = 0; i < 32; i += 4) {
+ /* Since the loads and stores are paired, allow the
+ copy to happen in the host endianness. */
+ tcg_gen_qemu_ld_i32(tmp, s_addr, da.mem_idx, MO_UL);
+ tcg_gen_qemu_st_i32(tmp, d_addr, da.mem_idx, MO_UL);
+ tcg_gen_add_tl(s_addr, s_addr, four);
+ tcg_gen_add_tl(d_addr, d_addr, four);
+ }
+
+ tcg_temp_free(s_addr);
+ tcg_temp_free(d_addr);
+ tcg_temp_free(four);
+ tcg_temp_free_i32(tmp);
+ }
+ break;
+#endif
default:
{
TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -2766,6 +2808,27 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv
addr,
gen_address_mask(dc, addr);
tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
break;
+ case GET_ASI_BFILL:
+ /* Store 32 bytes of T64 to ADDR. */
+ /* ??? The original qemu code suggests 8-byte alignment, dropping
+ the low bits, but the only place I can see this used is in the
+ Linux kernel with 32 byte alignment, which would make more sense
+ as a cacheline-style operation. */
+ {
+ TCGv d_addr = tcg_temp_new();
+ TCGv eight = tcg_const_tl(8);
+ int i;
+
+ tcg_gen_andi_tl(d_addr, addr, -8);
+ for (i = 0; i < 32; i += 8) {
+ tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
+ tcg_gen_add_tl(d_addr, d_addr, eight);
+ }
+
+ tcg_temp_free(d_addr);
+ tcg_temp_free(eight);
+ }
+ break;
default:
{
TCGv_i32 r_asi = tcg_const_i32(da.asi);
--
2.7.4
- [Qemu-devel] [PATCH v3 00/15] target-sparc improvements, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 01/15] target-sparc: Use overalignment flags for twinx and block asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 14/15] target-sparc: Use tcg_gen_atomic_xchg_tl, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 13/15] target-sparc: Remove MMU_MODE*_SUFFIX, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 11/15] target-sparc: Implement ldqf and stqf inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 10/15] target-sparc: Remove asi helper code handled inline, Richard Henderson, 2016/10/27
- Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements, Mark Cave-Ayland, 2016/10/28
- Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements, Artyom Tarasenko, 2016/10/31