[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_t
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl |
Date: |
Thu, 27 Oct 2016 10:07:32 -0700 |
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 31 +++++++------------------------
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4c0346c..1ef2654 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2391,31 +2391,21 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst,
TCGv src,
}
}
-static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpr,
+static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEUL);
- TCGv cmpv, oldv, tmpv;
+ TCGv oldv;
switch (da.type) {
case GET_ASI_EXCP:
return;
case GET_ASI_DIRECT:
- cmpv = tcg_temp_new();
oldv = tcg_temp_new();
- tmpv = tcg_temp_new();
- tcg_gen_ext32u_tl(cmpv, cmpr);
-
- /* ??? Should be atomic. */
- tcg_gen_qemu_ld_tl(oldv, addr, da.mem_idx, da.memop);
- tcg_gen_movcond_tl(TCG_COND_EQ, tmpv, oldv, cmpv,
- gen_load_gpr(dc, rd), oldv);
- tcg_gen_qemu_st_tl(tmpv, addr, da.mem_idx, da.memop);
-
+ tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
+ da.mem_idx, da.memop);
gen_store_gpr(dc, rd, oldv);
- tcg_temp_free(cmpv);
tcg_temp_free(oldv);
- tcg_temp_free(tmpv);
break;
default:
/* ??? Should be DAE_invalid_asi. */
@@ -2770,24 +2760,17 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr,
TCGv cmpv,
int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEQ);
- TCGv oldv, tmpv;
+ TCGv oldv;
switch (da.type) {
case GET_ASI_EXCP:
return;
case GET_ASI_DIRECT:
oldv = tcg_temp_new();
- tmpv = tcg_temp_new();
-
- /* ??? Should be atomic. */
- tcg_gen_qemu_ld_tl(oldv, addr, da.mem_idx, da.memop);
- tcg_gen_movcond_tl(TCG_COND_EQ, tmpv, oldv, cmpv,
- gen_load_gpr(dc, rd), oldv);
- tcg_gen_qemu_st_tl(tmpv, addr, da.mem_idx, da.memop);
-
+ tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
+ da.mem_idx, da.memop);
gen_store_gpr(dc, rd, oldv);
tcg_temp_free(oldv);
- tcg_temp_free(tmpv);
break;
default:
/* ??? Should be DAE_invalid_asi. */
--
2.7.4
- [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, (continued)
- [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 05/15] target-sparc: Handle more twinx asis, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 14/15] target-sparc: Use tcg_gen_atomic_xchg_tl, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 13/15] target-sparc: Remove MMU_MODE*_SUFFIX, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 11/15] target-sparc: Implement ldqf and stqf inline, Richard Henderson, 2016/10/27
- [Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 10/15] target-sparc: Remove asi helper code handled inline, Richard Henderson, 2016/10/27
- Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements, Mark Cave-Ayland, 2016/10/28
- Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements, Artyom Tarasenko, 2016/10/31