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Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 su
From: |
Artyom Tarasenko |
Subject: |
Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation |
Date: |
Wed, 12 Oct 2016 13:58:48 +0200 |
On Tue, Oct 11, 2016 at 11:52 PM, Mark Cave-Ayland
<address@hidden> wrote:
> On 01/10/16 11:05, Artyom Tarasenko wrote:
>
>> This patch series adds a Niagara OpenSPARC T1 sun4v machine.
>> The most important new feature: it can boot Solaris 10 / sparc64.
>> The machine uses a firmware released by Sun as a part of the OpenSPARC
>> project.
>>
>> The series are available under:
>> https://github.com/artyom-tarasenko/qemu/tree/sun4v-for-upstream
>>
>> The command line for booting Solaris 10 / sparc:
>>
>> sparc64-softmmu/qemu-system-sparc64 -M Niagara -L /path/to/S10image/
>> -nographic -m 256 -drive
>> if=pflash,readonly=on,file=/path/to/S10image/disk.s10hw2
>>
>> More info under
>> http://tyom.blogspot.de/2016/10/qemu-sun4vniagara-target-went-public.html
>>
>> Artyom Tarasenko (29):
>> target-sparc: don't trap on MMU-fault if MMU is disabled
>> target-sparc: use explicit mmu register pointers
>> target-sparc: add UA2005 TTE bit #defines
>> target-sparc: add UltraSPARC T1 TLB #defines
>> target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in
>> hypervisor mode
>> target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE
>> target-sparc: implement UA2005 scratchpad registers
>> target-sparc: implement UltraSPARC-T1 Strand status ASR
>> target-sparc: hypervisor mode takes over nucleus mode
>> target-sparc: implement UA2005 hypervisor traps
>> target-sparc: implement UA2005 GL register
>> target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
>> target-sparc: fix immediate UA2005 traps
>> target-sparc: use direct address translation in hyperprivileged mode
>> target-sparc: allow priveleged ASIs in hyperprivileged mode
>> target-sparc: ignore writes to UA2005 CPU mondo queue register
>> target-sparc: replace the last tlb entry when no free entries left
>> target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
>> target-sparc: implement UA2005 TSB Pointers
>> target-sparc: simplify ultrasparc_tsb_pointer
>> target-sparc: allow 256M sized pages
>> target-sparc: implement auto-demapping for UA2005 CPUs
>> target-sparc: implement ST_BLKINIT_ ASIs
>> target-sparc: add more registers to dump_mmu
>> target-sparc: implement UA2005 ASI_MMU (0x21)
>> target-sparc: store the UA2005 entries in sun4u format
>> target-sparc: implement sun4v RTC
>> target-sparc: move common cpu initialisation routines to sparc64.c
>> target-sparc: fix up Niagara machine
>>
>> MAINTAINERS | 6 +
>> default-configs/sparc64-softmmu.mak | 2 +
>> hw/sparc64/Makefile.objs | 2 +
>> hw/sparc64/niagara.c | 177 ++++++++++++++++
>> hw/sparc64/sparc64.c | 378
>> +++++++++++++++++++++++++++++++++++
>> hw/sparc64/sun4u.c | 382
>> +----------------------------------
>> hw/timer/Makefile.objs | 2 +
>> hw/timer/sun4v-rtc.c | 103 ++++++++++
>> include/hw/sparc/sparc64.h | 5 +
>> include/hw/timer/sun4v-rtc.h | 1 +
>> target-sparc/asi.h | 1 +
>> target-sparc/cpu.c | 13 +-
>> target-sparc/cpu.h | 79 +++++---
>> target-sparc/helper.h | 1 +
>> target-sparc/int64_helper.c | 42 +++-
>> target-sparc/ldst_helper.c | 388
>> ++++++++++++++++++++++++++++--------
>> target-sparc/machine.c | 4 +-
>> target-sparc/mmu_helper.c | 28 +--
>> target-sparc/translate.c | 42 +++-
>> target-sparc/win_helper.c | 46 ++++-
>> 20 files changed, 1171 insertions(+), 531 deletions(-)
>> create mode 100644 hw/sparc64/niagara.c
>> create mode 100644 hw/sparc64/sparc64.c
>> create mode 100644 hw/timer/sun4v-rtc.c
>> create mode 100644 include/hw/sparc/sparc64.h
>> create mode 100644 include/hw/timer/sun4v-rtc.h
>
> In general I think this is a great patchset, although obviously Richard
> has further comments on inner workings - excellent job! My only minor
> nit is whether -M Niagara should be lower-case to match the rest of the
> machine names.
I kept it the way it had been originally introduced, but am ok with changing it.
> One improvement I'd like to see is a patch to update the documentation
> to reflect the new sun4v machine, in particular covering where to get
> hold of the PROM/disk images as per the final commit message.
You mean the target-sparc/TODO, or is there more documentation?
I'd rather put it on the http://wiki.qemu.org/SPARC page.
> And also
> does it make sense for us to try and distribute parts of the ROM images
> with QEMU, and if so which parts and can we legally do that?
Good question. I'm not a lawyer, so I had no plans on distributing them.
> Finally my current understanding is that the atomics/target-sparc
> patches will go in first and then this patchset will be rebased upon
> those - is that correct? If so, I'll wait for the rebased version before
> I give it a thorough test over my sun4u images.
Ok. I'm off till the end of October, so let's postpone this series
till November or so.
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
- Re: [Qemu-devel] [PATCH 26/29] target-sparc: store the UA2005 entries in sun4u format, (continued)
- [Qemu-devel] [PATCH 27/29] target-sparc: implement sun4v RTC, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 28/29] target-sparc: move common cpu initialisation routines to sparc64.c, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 29/29] target-sparc: fix up Niagara machine, Artyom Tarasenko, 2016/10/01
- Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation, no-reply, 2016/10/01
- Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation, Mark Cave-Ayland, 2016/10/11
- Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation,
Artyom Tarasenko <=