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[Qemu-devel] [PATCH 27/29] target-sparc: implement sun4v RTC
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PATCH 27/29] target-sparc: implement sun4v RTC |
Date: |
Sat, 1 Oct 2016 12:05:31 +0200 |
Signed-off-by: Artyom Tarasenko <address@hidden>
---
MAINTAINERS | 6 +++
hw/timer/Makefile.objs | 2 +
hw/timer/sun4v-rtc.c | 103 +++++++++++++++++++++++++++++++++++++++++++
include/hw/timer/sun4v-rtc.h | 1 +
4 files changed, 112 insertions(+)
create mode 100644 hw/timer/sun4v-rtc.c
create mode 100644 include/hw/timer/sun4v-rtc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9b7e846..2866d17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1014,6 +1014,12 @@ M: Dmitry Fleytman <address@hidden>
S: Maintained
F: hw/net/e1000e*
+sun4v RTC
+M: Artyom Tarasenko <address@hidden>
+S: Maintained
+F: hw/timer/sun4v-rtc.c
+F: include/hw/timer/sun4v-rtc.h
+
Subsystems
----------
Audio
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..c1e93a3 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -34,3 +34,5 @@ obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
+
+common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
diff --git a/hw/timer/sun4v-rtc.c b/hw/timer/sun4v-rtc.c
new file mode 100644
index 0000000..bd41e95
--- /dev/null
+++ b/hw/timer/sun4v-rtc.c
@@ -0,0 +1,103 @@
+/*
+ * QEMU sun4v Real Time Clock device
+ *
+ * The sun4v_rtc device (sun4v tod clock)
+ *
+ * Copyright (c) 2016 Artyom Tarasenko
+ *
+ * This code is licensed under the GNU GPL v3 or (at your option) any later
+ * version.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/timer/sun4v-rtc.h"
+
+//#define DEBUG_SUN4V_RTC
+
+#ifdef DEBUG_SUN4V_RTC
+#define DPRINTF(fmt, ...) \
+ do { printf("sun4v_rtc: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define TYPE_SUN4V_RTC "sun4v_rtc"
+#define SUN4V_RTC(obj) OBJECT_CHECK(Sun4vRtc, (obj), TYPE_SUN4V_RTC)
+
+typedef struct Sun4vRtc {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+} Sun4vRtc;
+
+static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ uint64_t val = qemu_clock_get_ms(QEMU_CLOCK_REALTIME) / 1000;
+ if (!(addr & 4ULL)) {
+ /* accessing the high 32 bits */
+ val >>= 32;
+ }
+ DPRINTF("read from " TARGET_FMT_plx " val %lx\n", addr, val);
+ return val;
+}
+
+static void sun4v_rtc_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
+}
+
+static const MemoryRegionOps sun4v_rtc_ops = {
+ .read = sun4v_rtc_read,
+ .write = sun4v_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+void sun4v_rtc_init(hwaddr addr)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ dev = qdev_create(NULL, TYPE_SUN4V_RTC);
+ s = SYS_BUS_DEVICE(dev);
+ SUN4V_RTC(dev);
+
+ qdev_init_nofail(dev);
+
+ sysbus_mmio_map(s, 0, addr);
+}
+
+static int sun4v_rtc_init1(SysBusDevice *dev)
+{
+ Sun4vRtc *s = SUN4V_RTC(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &sun4v_rtc_ops, s,
+ "sun4v-rtc", 0x08ULL);
+ sysbus_init_mmio(dev, &s->iomem);
+ return 0;
+}
+
+static void sun4v_rtc_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = sun4v_rtc_init1;
+}
+
+static const TypeInfo sun4v_rtc_info = {
+ .name = TYPE_SUN4V_RTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Sun4vRtc),
+ .class_init = sun4v_rtc_class_init,
+};
+
+static void sun4v_rtc_register_types(void)
+{
+ type_register_static(&sun4v_rtc_info);
+}
+
+type_init(sun4v_rtc_register_types)
diff --git a/include/hw/timer/sun4v-rtc.h b/include/hw/timer/sun4v-rtc.h
new file mode 100644
index 0000000..407278f
--- /dev/null
+++ b/include/hw/timer/sun4v-rtc.h
@@ -0,0 +1 @@
+void sun4v_rtc_init(hwaddr addr);
--
2.7.2
- Re: [Qemu-devel] [PATCH 22/29] target-sparc: implement auto-demapping for UA2005 CPUs, (continued)
- [Qemu-devel] [PATCH 24/29] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 23/29] target-sparc: implement ST_BLKINIT_ ASIs, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 25/29] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 26/29] target-sparc: store the UA2005 entries in sun4u format, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 27/29] target-sparc: implement sun4v RTC,
Artyom Tarasenko <=
- [Qemu-devel] [PATCH 28/29] target-sparc: move common cpu initialisation routines to sparc64.c, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 29/29] target-sparc: fix up Niagara machine, Artyom Tarasenko, 2016/10/01
- Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation, no-reply, 2016/10/01
- Re: [Qemu-devel] [PATCH 00/29] target-sparc: add Niagara OpenSPARC T1 sun4v emulation, Mark Cave-Ayland, 2016/10/11