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[Qemu-devel] [PULL v3 16/18] target-aarch64: Generate fences for aarch64
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL v3 16/18] target-aarch64: Generate fences for aarch64 |
Date: |
Mon, 12 Sep 2016 16:39:50 -0700 |
From: Pranith Kumar <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f5e29d2..09877bc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1305,7 +1305,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
return;
case 4: /* DSB */
case 5: /* DMB */
- /* We don't emulate caches so barriers are no-ops */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
return;
case 6: /* ISB */
/* We need to break the TB after this insn to execute
@@ -1934,7 +1934,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t
insn)
if (!is_store) {
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
} else {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
}
} else {
@@ -1943,11 +1949,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t
insn)
/* Generate ISS for non-exclusive accesses including LASR. */
if (is_store) {
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ }
do_gpr_st(s, tcg_rt, tcg_addr, size,
true, rt, iss_sf, is_lasr);
} else {
do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
true, rt, iss_sf, is_lasr);
+ if (is_lasr) {
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
}
}
}
--
2.7.4
- [Qemu-devel] [PULL v3 04/18] Introduce TCGOpcode for memory barrier, (continued)
- [Qemu-devel] [PULL v3 04/18] Introduce TCGOpcode for memory barrier, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 07/18] tcg/arm: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 11/18] tcg/s390: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 10/18] tcg/ppc: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 14/18] target-arm: Generate fences in ARMv7 frontend, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 15/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 16/18] target-aarch64: Generate fences for aarch64,
Richard Henderson <=
- [Qemu-devel] [PULL v3 18/18] tcg: Optimize fence instructions, Richard Henderson, 2016/09/12
- [Qemu-devel] [PULL v3 17/18] target-i386: Generate fences for x86, Richard Henderson, 2016/09/12
- Re: [Qemu-devel] [PULL v3 00/18] tcg queued patches, Peter Maydell, 2016/09/13