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[Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruct
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction |
Date: |
Mon, 12 Sep 2016 12:11:42 +0530 |
stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 3 +++
target-ppc/translate/vsx-ops.inc.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7a4b488..eb681de 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2542,6 +2542,8 @@ static void glue(gen_qemu_, glue(stop,
_i64))(DisasContext *ctx, \
tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
}
+GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
+GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 888f2e4..eee6052 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -118,6 +118,9 @@ static void gen_##name(DisasContext *ctx)
\
}
VSX_STORE_SCALAR(stxsdx, st64_i64)
+
+VSX_STORE_SCALAR(stxsibx, st8_i64)
+VSX_STORE_SCALAR(stxsihx, st16_i64)
VSX_STORE_SCALAR(stxsiwx, st32_i64)
VSX_STORE_SCALAR(stxsspx, st32fs)
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 4cd742c..414b73b 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -9,6 +9,8 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxsihx, 0x1F, 0xD, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
--
2.7.4
- [Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur to use new macro, (continued)
- [Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 07/17] target-ppc: consolidate load with reservation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 12/17] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 14/17] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/09/12