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[Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store opera
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations |
Date: |
Mon, 12 Sep 2016 12:11:33 +0530 |
Implement macro to consolidate store operations using newer
tcg_gen_qemu_st function.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0d27067..f228ae0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2498,30 +2498,27 @@ GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
#endif
-static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
+#define GEN_QEMU_STORE_TL(stop, op) \
+static void glue(gen_qemu_, stop)(DisasContext *ctx, \
+ TCGv val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
-static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
+GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
+GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
-static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
+#define GEN_QEMU_STORE_64(stop, op) \
+static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
+ TCGv_i64 val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
}
-static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
-{
- TCGv tmp = tcg_temp_new();
- tcg_gen_trunc_i64_tl(tmp, val);
- gen_qemu_st32(ctx, tmp, addr);
- tcg_temp_free(tmp);
-}
+GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
--
2.7.4
- [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 01/17] target-ppc: consolidate load operations, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/09/12
- [Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction, Nikunj A Dadhania, 2016/09/12