[Qemu-devel] [PULL v2 00/18] tcg queued patches

[Richard Henderson]

Three unrelated patches and Pranith's memory barrier patch sets.

The alignment patch is in support of Sparc's ldf instructions:
8 and 16-byte memory operations that require only 4-byte alignment.
It's just as easy to support this kind of misalignment as any other.
As mentioned in the commit, we'd also forgotten to properly handle
arm32, mips, ia64 and sparc when it came to overalignment.

I have a follow up patch set to make use of this for target-sparc.

I've tweaked the memory barrier patch set.  For aarch64, ppc
and sparc, I've fixed the insn selection a bit.  I merged the
optimization pass into the current optimization pass.


r~


[v2: With actual pull data this time, cover letter only.]


The following changes since commit 2926375cffce464fde6b4dabaed1e133d549af39:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging 
(2016-09-06 17:18:17 +0100)

are available in the git repository at:

  git://github.com/rth7680/qemu.git tags/pull-tcg-20160908

for you to fetch changes up to a36ae2f6ad489d510ada40bf2aab9539e4a97511:

  tcg: Optimize fence instructions (2016-09-07 13:46:01 -0700)

----------------------------------------------------------------
Alignment, memory barrier, and misc patches.

----------------------------------------------------------------
Pranith Kumar (15):
      Introduce TCGOpcode for memory barrier
      tcg/i386: Add support for fence
      tcg/aarch64: Add support for fence
      tcg/arm: Add support for fence
      tcg/ia64: Add support for fence
      tcg/mips: Add support for fence
      tcg/ppc: Add support for fence
      tcg/s390: Add support for fence
      tcg/sparc: Add support for fence
      tcg/tci: Add support for fence
      target-arm: Generate fences in ARMv7 frontend
      target-alpha: Generate fence op
      target-aarch64: Generate fences for aarch64
      target-i386: Generate fences for x86
      tcg: Optimize fence instructions

Richard Henderson (3):
      tcg: Support arbitrary size + alignment
      tcg: Merge GETPC and GETRA
      cpu-exec: Check -dfilter for -d cpu

 cpu-exec.c                   |  3 +-
 cputlb.c                     |  6 ++--
 include/exec/exec-all.h      |  9 ++---
 softmmu_template.h           | 48 ++++++++------------------
 target-alpha/translate.c     |  4 +--
 target-arm/helper.c          |  6 ++--
 target-arm/translate-a64.c   | 14 +++++++-
 target-arm/translate.c       |  4 +--
 target-i386/translate.c      |  8 +++++
 target-mips/op_helper.c      | 18 +++++-----
 tcg/README                   | 17 ++++++++++
 tcg/aarch64/tcg-target.inc.c | 35 +++++++++++++++----
 tcg/arm/tcg-target.inc.c     | 37 ++++++++++++++++----
 tcg/i386/tcg-target.inc.c    | 33 +++++++++++++-----
 tcg/ia64/tcg-target.inc.c    | 27 +++++++++++----
 tcg/mips/tcg-target.inc.c    | 18 ++++++++--
 tcg/optimize.c               | 54 +++++++++++++++++++++++++++++
 tcg/ppc/tcg-target.inc.c     | 78 +++++++++++++++++++++++++++---------------
 tcg/s390/tcg-target.inc.c    | 24 ++++++++-----
 tcg/sparc/tcg-target.inc.c   | 30 ++++++++++++----
 tcg/tcg-op.c                 | 17 ++++++++++
 tcg/tcg-op.h                 |  2 ++
 tcg/tcg-opc.h                |  2 ++
 tcg/tcg.h                    | 81 +++++++++++++++++++++++++++-----------------
 tcg/tci/tcg-target.inc.c     |  3 ++
 tci.c                        |  4 +++
 translate-all.c              |  1 +
 user-exec.c                  |  7 ++--
 28 files changed, 421 insertions(+), 169 deletions(-)