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[Qemu-devel] [PULL 10/18] tcg/ppc: Add support for fence
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 10/18] tcg/ppc: Add support for fence |
Date: |
Wed, 7 Sep 2016 14:10:40 -0700 |
From: Pranith Kumar <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc/tcg-target.inc.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 82ac4b3..4aee8ea 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -469,6 +469,10 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STHX XO31(407)
#define STWX XO31(151)
+#define EIEIO XO31(854)
+#define HWSYNC XO31(598)
+#define LWSYNC (HWSYNC | (1u << 21))
+
#define SPR(a, b) ((((a)<<5)|(b))<<11)
#define LR SPR(8, 0)
#define CTR SPR(9, 0)
@@ -1243,6 +1247,18 @@ static void tcg_out_brcond2 (TCGContext *s, const TCGArg
*args,
tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
}
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ uint32_t insn = HWSYNC;
+ a0 &= TCG_MO_ALL;
+ if (a0 == TCG_MO_LD_LD) {
+ insn = LWSYNC;
+ } else if (a0 == TCG_MO_ST_ST) {
+ insn = EIEIO;
+ }
+ tcg_out32(s, insn);
+}
+
#ifdef __powerpc64__
void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
{
@@ -2452,6 +2468,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2599,6 +2619,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
#endif
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.7.4
- [Qemu-devel] [PULL 00/18] tcg queued patches, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 03/18] cpu-exec: Check -dfilter for -d cpu, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 02/18] tcg: Merge GETPC and GETRA, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 01/18] tcg: Support arbitrary size + alignment, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 05/18] tcg/i386: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 06/18] tcg/aarch64: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 04/18] Introduce TCGOpcode for memory barrier, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 07/18] tcg/arm: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 10/18] tcg/ppc: Add support for fence,
Richard Henderson <=
- [Qemu-devel] [PULL 11/18] tcg/s390: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 15/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 14/18] target-arm: Generate fences in ARMv7 frontend, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 16/18] target-aarch64: Generate fences for aarch64, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 17/18] target-i386: Generate fences for x86, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 18/18] tcg: Optimize fence instructions, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL v2 00/18] tcg queued patches, Richard Henderson, 2016/09/08