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Re: [Qemu-devel] [PATCH v1 02/10] target-ppc: consolidate load operation
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [PATCH v1 02/10] target-ppc: consolidate load operations |
Date: |
Fri, 12 Aug 2016 10:22:16 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 08/10/2016 08:00 PM, Nikunj A Dadhania wrote:
>> +#define GEN_QEMU_LOAD_64(ldop, op) \
>> +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
>> + TCGv_i64 val, \
>> + TCGv addr) \
>> +{ \
>> + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \
>> + op | ctx->default_tcg_memop_mask); \
>> +}
>> +
>> +GEN_QEMU_LOAD_64(ld32u, MO_UL)
>> +GEN_QEMU_LOAD_64(ld32s, MO_SL)
>>
>> static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv
>> arg2)
>> {
>
> You can of course include this last function in the cleanup as well.
Let me do this as separate patch, as it will need patching at lot of
places. This will be function name change: gen_qemu_ld64 =>
gen_qemu_ld64_i64
I have one more patch converting load/store with reservation to
qemu_st/ld.
Regards,
Nikunj
[Qemu-devel] [PATCH v1 03/10] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 04/10] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 08/10] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 10/10] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 07/10] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/08/10