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[Qemu-devel] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction |
Date: |
Thu, 11 Aug 2016 00:31:01 +0530 |
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed
lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 2 ++
target-ppc/translate/vsx-impl.inc.c | 2 ++
target-ppc/translate/vsx-ops.inc.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 67eac9f..1fc78d9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2503,6 +2503,8 @@ static void glue(gen_qemu_, glue(ldop,
_i64))(DisasContext *ctx, \
op | ctx->default_tcg_memop_mask); \
}
+GEN_QEMU_LOAD_64(ld8u, MO_UB)
+GEN_QEMU_LOAD_64(ld16u, MO_UW)
GEN_QEMU_LOAD_64(ld32u, MO_UL)
GEN_QEMU_LOAD_64(ld32s, MO_SL)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 43d073e..9cb48e1 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -36,6 +36,8 @@ static void gen_##name(DisasContext *ctx)
\
VSX_LOAD_SCALAR(lxsdx, ld64)
VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
+VSX_LOAD_SCALAR(lxsibzx, ld8u_i64)
+VSX_LOAD_SCALAR(lxsihzx, ld16u_i64)
VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
VSX_LOAD_SCALAR(lxsspx, ld32fs)
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 9c98795..4f32837 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -1,6 +1,8 @@
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
--
2.7.4
- [Qemu-devel] [PATCH v1 01/10] target-ppc: add xxspltib instruction, (continued)
[Qemu-devel] [PATCH v1 03/10] target-ppc: consolidate store operations, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 06/10] target-ppc: add stxsi[bh]x instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 05/10] target-ppc: add lxsi[bw]zx instruction,
Nikunj A Dadhania <=
[Qemu-devel] [PATCH v1 04/10] target-ppc: Implement darn instruction, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 08/10] target-ppc: add lxvb16x and lxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 10/10] target-ppc: add stxvb16x and stxvh8x, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 07/10] target-ppc: improve lxvw4x implementation, Nikunj A Dadhania, 2016/08/10
[Qemu-devel] [PATCH v1 09/10] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/08/10