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[Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOM
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOMMU IR |
Date: |
Thu, 21 Jul 2016 20:52:30 +0300 |
From: Peter Xu <address@hidden>
Several data structs are defined to better support the rest of the
patches: IRTE to parse remapping table entries, and IOAPIC/MSI related
structure bits to parse interrupt entries to be filled in by guest
kernel.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
include/hw/i386/intel_iommu.h | 74 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index ce515c4..260aa8e 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -52,6 +52,8 @@ typedef struct IntelIOMMUState IntelIOMMUState;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
typedef struct VTDBus VTDBus;
+typedef union VTD_IRTE VTD_IRTE;
+typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
/* Context-Entry */
struct VTDContextEntry {
@@ -90,6 +92,78 @@ struct VTDIOTLBEntry {
bool write_flags;
};
+/* Interrupt Remapping Table Entry Definition */
+union VTD_IRTE {
+ struct {
+#ifdef HOST_WORDS_BIGENDIAN
+ uint32_t dest_id:32; /* Destination ID */
+ uint32_t __reserved_1:8; /* Reserved 1 */
+ uint32_t vector:8; /* Interrupt Vector */
+ uint32_t irte_mode:1; /* IRTE Mode */
+ uint32_t __reserved_0:3; /* Reserved 0 */
+ uint32_t __avail:4; /* Available spaces for software */
+ uint32_t delivery_mode:3; /* Delivery Mode */
+ uint32_t trigger_mode:1; /* Trigger Mode */
+ uint32_t redir_hint:1; /* Redirection Hint */
+ uint32_t dest_mode:1; /* Destination Mode */
+ uint32_t fault_disable:1; /* Fault Processing Disable */
+ uint32_t present:1; /* Whether entry present/available */
+#else
+ uint32_t present:1; /* Whether entry present/available */
+ uint32_t fault_disable:1; /* Fault Processing Disable */
+ uint32_t dest_mode:1; /* Destination Mode */
+ uint32_t redir_hint:1; /* Redirection Hint */
+ uint32_t trigger_mode:1; /* Trigger Mode */
+ uint32_t delivery_mode:3; /* Delivery Mode */
+ uint32_t __avail:4; /* Available spaces for software */
+ uint32_t __reserved_0:3; /* Reserved 0 */
+ uint32_t irte_mode:1; /* IRTE Mode */
+ uint32_t vector:8; /* Interrupt Vector */
+ uint32_t __reserved_1:8; /* Reserved 1 */
+ uint32_t dest_id:32; /* Destination ID */
+#endif
+ uint16_t source_id:16; /* Source-ID */
+#ifdef HOST_WORDS_BIGENDIAN
+ uint64_t __reserved_2:44; /* Reserved 2 */
+ uint64_t sid_vtype:2; /* Source-ID Validation Type */
+ uint64_t sid_q:2; /* Source-ID Qualifier */
+#else
+ uint64_t sid_q:2; /* Source-ID Qualifier */
+ uint64_t sid_vtype:2; /* Source-ID Validation Type */
+ uint64_t __reserved_2:44; /* Reserved 2 */
+#endif
+ } QEMU_PACKED;
+ uint64_t data[2];
+};
+
+#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
+#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
+
+/* Programming format for MSI/MSI-X addresses */
+union VTD_IR_MSIAddress {
+ struct {
+#ifdef HOST_WORDS_BIGENDIAN
+ uint32_t __head:12; /* Should always be: 0x0fee */
+ uint32_t index_l:15; /* Interrupt index bit 14-0 */
+ uint32_t int_mode:1; /* Interrupt format */
+ uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
+ uint32_t index_h:1; /* Interrupt index bit 15 */
+ uint32_t __not_care:2;
+#else
+ uint32_t __not_care:2;
+ uint32_t index_h:1; /* Interrupt index bit 15 */
+ uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
+ uint32_t int_mode:1; /* Interrupt format */
+ uint32_t index_l:15; /* Interrupt index bit 14-0 */
+ uint32_t __head:12; /* Should always be: 0x0fee */
+#endif
+ } QEMU_PACKED;
+ uint32_t data;
+};
+
+/* When IR is enabled, all MSI/MSI-X data bits should be zero */
+#define VTD_IR_MSI_DATA (0)
+
/* The iommu (DMAR) device state struct */
struct IntelIOMMUState {
X86IOMMUState x86_iommu;
--
MST
- [Qemu-devel] [PULL v5 09/57] x86-iommu: introduce parent class, (continued)
- [Qemu-devel] [PULL v5 09/57] x86-iommu: introduce parent class, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 10/57] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 11/57] x86-iommu: provide x86_iommu_get_default, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 12/57] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 13/57] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 14/57] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 16/57] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 17/57] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 18/57] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOMMU IR,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 23/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 24/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 25/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/21