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[Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defi
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines |
Date: |
Thu, 21 Jul 2016 20:52:35 +0300 |
From: Peter Xu <address@hidden>
Adding translation fault definitions for interrupt remapping. Please
refer to VT-d spec section 7.1.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/intel_iommu_internal.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 309833f..2a9987f 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -271,6 +271,19 @@ typedef enum VTDFaultReason {
* context-entry.
*/
VTD_FR_CONTEXT_ENTRY_TT,
+
+ /* Interrupt remapping transition faults */
+ VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved
+ * fields set */
+ VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */
+ VTD_FR_IR_ENTRY_P = 0x22, /* Present (P) not set in IRTE */
+ VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */
+ VTD_FR_IR_IRTE_RSVD = 0x24, /* IRTE Rsvd field non-zero with
+ * Present flag set */
+ VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR
+ * request while disabled */
+ VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
+
/* This is not a normal fault reason. We use this to indicate some faults
* that are not referenced by the VT-d specification.
* Fault event with such reason should not be recorded.
--
MST
- [Qemu-devel] [PULL v5 10/57] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, (continued)
- [Qemu-devel] [PULL v5 10/57] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 11/57] x86-iommu: provide x86_iommu_get_default, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 12/57] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 13/57] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 14/57] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 16/57] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 17/57] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 18/57] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v5 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 23/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 24/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 25/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/21