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[Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based o
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode |
Date: |
Tue, 7 Jun 2016 12:50:20 +1000 |
We used to always flush the TLB when changing relocation mode in
MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).
We don't anymore since we have split mmu_idx for instruction and data.
However, since we hard code the mmu_idx in the translated code, we
now need to also make sure MSR:IR and MSR:DR are part of the hflags
used to tag translated code, so that we use different translated
code for different MMU settings.
Darwin gets hurt by this problem.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/helper_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 12af61c..104b690 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
/* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
- (1 << MSR_LE) | (1 << MSR_VSX);
+ (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
--
2.5.5
- [Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode,
Benjamin Herrenschmidt <=
- [Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, Benjamin Herrenschmidt, 2016/06/06