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Re: [Qemu-devel] [PATCH 1/2] target-arm: Set IL bit in syndromes for ins

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep
Date: Tue, 17 May 2016 14:06:28 +0100

On 17 May 2016 at 13:50, Edgar E. Iglesias <address@hidden> wrote:
> On Tue, May 17, 2016 at 01:14:17PM +0100, Peter Maydell wrote:
>> For some exception syndrome types, the IL bit should always be set.
>> This includes the instruction abort, watchpoint and software step
>> syndrome types; add the missing ARM_EL_IL bit to the syndrome
>> values returned by syn_insn_abort(), syn_swstep() and syn_watchpoint().

> Maybe we should have a reference in a comment to the table in
> the pseudo code for AArch64.ExceptionClass?
> It makes it a little easier to understand some of these settings...

I just used the text parts of the ARM ARM as reference for this one,
not the pseudocode (specifically, D7.2.27, the ESR_ELx register description,
has the definition of the IL bit and says which exceptions have IL set).
I think for pretty much any feature in the emulation you need to
look it up in the ARM ARM to understand what it's doing, and we
could end up with cross-references every other line...

-- PMM

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